2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
28 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
32 #if defined(__cplusplus)
36 struct drm_nouveau_channel_alloc {
37 uint32_t fb_ctxdma_handle;
38 uint32_t tt_ctxdma_handle;
41 uint32_t pushbuf_domains;
44 uint32_t notifier_handle;
46 /* DRM-enforced subchannel assignments */
54 struct drm_nouveau_channel_free {
58 struct drm_nouveau_grobj_alloc {
64 struct drm_nouveau_notifierobj_alloc {
71 struct drm_nouveau_gpuobj_free {
76 #define NOUVEAU_GETPARAM_PCI_VENDOR 3
77 #define NOUVEAU_GETPARAM_PCI_DEVICE 4
78 #define NOUVEAU_GETPARAM_BUS_TYPE 5
79 #define NOUVEAU_GETPARAM_FB_SIZE 8
80 #define NOUVEAU_GETPARAM_AGP_SIZE 9
81 #define NOUVEAU_GETPARAM_CHIPSET_ID 11
82 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
83 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13
84 #define NOUVEAU_GETPARAM_PTIMER_TIME 14
85 #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
86 #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
87 struct drm_nouveau_getparam {
92 struct drm_nouveau_setparam {
97 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
98 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
99 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
100 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
101 #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
103 #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
104 #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
105 #define NOUVEAU_GEM_TILE_16BPP 0x00000001
106 #define NOUVEAU_GEM_TILE_32BPP 0x00000002
107 #define NOUVEAU_GEM_TILE_ZETA 0x00000004
108 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
110 struct drm_nouveau_gem_info {
120 struct drm_nouveau_gem_new {
121 struct drm_nouveau_gem_info info;
126 #define NOUVEAU_GEM_MAX_BUFFERS 1024
127 struct drm_nouveau_gem_pushbuf_bo_presumed {
133 struct drm_nouveau_gem_pushbuf_bo {
139 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
142 #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
143 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
144 #define NOUVEAU_GEM_RELOC_OR (1 << 2)
145 #define NOUVEAU_GEM_MAX_RELOCS 1024
146 struct drm_nouveau_gem_pushbuf_reloc {
147 __u32 reloc_bo_index;
148 __u32 reloc_bo_offset;
156 #define NOUVEAU_GEM_MAX_PUSH 512
157 struct drm_nouveau_gem_pushbuf_push {
164 struct drm_nouveau_gem_pushbuf {
174 #define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
175 __u64 vram_available;
176 __u64 gart_available;
179 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
180 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
181 struct drm_nouveau_gem_cpu_prep {
186 struct drm_nouveau_gem_cpu_fini {
190 #define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
191 #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
192 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
193 #define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
194 #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
195 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
196 #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
197 #define DRM_NOUVEAU_NVIF 0x07
198 #define DRM_NOUVEAU_SVM_INIT 0x08
199 #define DRM_NOUVEAU_SVM_BIND 0x09
200 #define DRM_NOUVEAU_GEM_NEW 0x40
201 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
202 #define DRM_NOUVEAU_GEM_CPU_PREP 0x42
203 #define DRM_NOUVEAU_GEM_CPU_FINI 0x43
204 #define DRM_NOUVEAU_GEM_INFO 0x44
206 struct drm_nouveau_svm_init {
207 __u64 unmanaged_addr;
208 __u64 unmanaged_size;
211 struct drm_nouveau_svm_bind {
222 #define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
223 #define NOUVEAU_SVM_BIND_COMMAND_BITS 8
224 #define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
225 #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
226 #define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
227 #define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
228 #define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
229 #define NOUVEAU_SVM_BIND_TARGET_BITS 32
230 #define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
233 * Below is use to validate ioctl argument, userspace can also use it to make
234 * sure that no bit are set beyond known fields for a given kernel version.
236 #define NOUVEAU_SVM_BIND_VALID_BITS 48
237 #define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
241 * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
242 * result: number of page successfuly migrate to the target memory.
244 #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
247 * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
249 #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
252 #if defined(__cplusplus)
256 #endif /* __NOUVEAU_DRM_H__ */