2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
26 #include <linux/delay.h>
27 #include <linux/i2c.h>
28 #include <linux/types.h>
31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
32 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
33 * 1.0 devices basically don't exist in the wild.
35 * Abbreviations, in chronological order:
37 * eDP: Embedded DisplayPort version 1
38 * DPI: DisplayPort Interoperability Guideline v1.1a
39 * 1.2: DisplayPort 1.2
40 * MST: Multistream Transport - part of DP 1.2a
42 * 1.2 formally includes both eDP and DPI definitions.
45 /* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
46 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
47 #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
48 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
49 #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
50 #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
51 /* bits per component for non-RAW */
52 #define DP_MSA_MISC_6_BPC (0 << 5)
53 #define DP_MSA_MISC_8_BPC (1 << 5)
54 #define DP_MSA_MISC_10_BPC (2 << 5)
55 #define DP_MSA_MISC_12_BPC (3 << 5)
56 #define DP_MSA_MISC_16_BPC (4 << 5)
57 /* bits per component for RAW */
58 #define DP_MSA_MISC_RAW_6_BPC (1 << 5)
59 #define DP_MSA_MISC_RAW_7_BPC (2 << 5)
60 #define DP_MSA_MISC_RAW_8_BPC (3 << 5)
61 #define DP_MSA_MISC_RAW_10_BPC (4 << 5)
62 #define DP_MSA_MISC_RAW_12_BPC (5 << 5)
63 #define DP_MSA_MISC_RAW_14_BPC (6 << 5)
64 #define DP_MSA_MISC_RAW_16_BPC (7 << 5)
65 /* pixel encoding/colorimetry format */
66 #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
67 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
68 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
69 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
70 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
71 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
72 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
73 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
74 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
75 #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
76 #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
77 #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
78 #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
79 #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
80 #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
81 #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
82 #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
83 #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
84 #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
85 #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
87 #define DP_AUX_MAX_PAYLOAD_BYTES 16
89 #define DP_AUX_I2C_WRITE 0x0
90 #define DP_AUX_I2C_READ 0x1
91 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
92 #define DP_AUX_I2C_MOT 0x4
93 #define DP_AUX_NATIVE_WRITE 0x8
94 #define DP_AUX_NATIVE_READ 0x9
96 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
97 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
98 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
99 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
101 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
102 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
103 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
104 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
106 /* AUX CH addresses */
108 #define DP_DPCD_REV 0x000
109 # define DP_DPCD_REV_10 0x10
110 # define DP_DPCD_REV_11 0x11
111 # define DP_DPCD_REV_12 0x12
112 # define DP_DPCD_REV_13 0x13
113 # define DP_DPCD_REV_14 0x14
115 #define DP_MAX_LINK_RATE 0x001
117 #define DP_MAX_LANE_COUNT 0x002
118 # define DP_MAX_LANE_COUNT_MASK 0x1f
119 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
120 # define DP_ENHANCED_FRAME_CAP (1 << 7)
122 #define DP_MAX_DOWNSPREAD 0x003
123 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
124 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
125 # define DP_TPS4_SUPPORTED (1 << 7)
127 #define DP_NORP 0x004
129 #define DP_DOWNSTREAMPORT_PRESENT 0x005
130 # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
131 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
132 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
133 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
134 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
135 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
136 # define DP_FORMAT_CONVERSION (1 << 3)
137 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
139 #define DP_MAIN_LINK_CHANNEL_CODING 0x006
140 # define DP_CAP_ANSI_8B10B (1 << 0)
142 #define DP_DOWN_STREAM_PORT_COUNT 0x007
143 # define DP_PORT_COUNT_MASK 0x0f
144 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
145 # define DP_OUI_SUPPORT (1 << 7)
147 #define DP_RECEIVE_PORT_0_CAP_0 0x008
148 # define DP_LOCAL_EDID_PRESENT (1 << 1)
149 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
151 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
153 #define DP_RECEIVE_PORT_1_CAP_0 0x00a
154 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
156 #define DP_I2C_SPEED_CAP 0x00c /* DPI */
157 # define DP_I2C_SPEED_1K 0x01
158 # define DP_I2C_SPEED_5K 0x02
159 # define DP_I2C_SPEED_10K 0x04
160 # define DP_I2C_SPEED_100K 0x08
161 # define DP_I2C_SPEED_400K 0x10
162 # define DP_I2C_SPEED_1M 0x20
164 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
165 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
166 # define DP_FRAMING_CHANGE_CAP (1 << 1)
167 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
169 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
170 # define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
171 # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
173 #define DP_ADAPTER_CAP 0x00f /* 1.2 */
174 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
175 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
177 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
178 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
180 /* Multiple stream transport */
181 #define DP_FAUX_CAP 0x020 /* 1.2 */
182 # define DP_FAUX_CAP_1 (1 << 0)
184 #define DP_MSTM_CAP 0x021 /* 1.2 */
185 # define DP_MST_CAP (1 << 0)
187 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
189 /* AV_SYNC_DATA_BLOCK 1.2 */
190 #define DP_AV_GRANULARITY 0x023
191 # define DP_AG_FACTOR_MASK (0xf << 0)
192 # define DP_AG_FACTOR_3MS (0 << 0)
193 # define DP_AG_FACTOR_2MS (1 << 0)
194 # define DP_AG_FACTOR_1MS (2 << 0)
195 # define DP_AG_FACTOR_500US (3 << 0)
196 # define DP_AG_FACTOR_200US (4 << 0)
197 # define DP_AG_FACTOR_100US (5 << 0)
198 # define DP_AG_FACTOR_10US (6 << 0)
199 # define DP_AG_FACTOR_1US (7 << 0)
200 # define DP_VG_FACTOR_MASK (0xf << 4)
201 # define DP_VG_FACTOR_3MS (0 << 4)
202 # define DP_VG_FACTOR_2MS (1 << 4)
203 # define DP_VG_FACTOR_1MS (2 << 4)
204 # define DP_VG_FACTOR_500US (3 << 4)
205 # define DP_VG_FACTOR_200US (4 << 4)
206 # define DP_VG_FACTOR_100US (5 << 4)
208 #define DP_AUD_DEC_LAT0 0x024
209 #define DP_AUD_DEC_LAT1 0x025
211 #define DP_AUD_PP_LAT0 0x026
212 #define DP_AUD_PP_LAT1 0x027
214 #define DP_VID_INTER_LAT 0x028
216 #define DP_VID_PROG_LAT 0x029
218 #define DP_REP_LAT 0x02a
220 #define DP_AUD_DEL_INS0 0x02b
221 #define DP_AUD_DEL_INS1 0x02c
222 #define DP_AUD_DEL_INS2 0x02d
223 /* End of AV_SYNC_DATA_BLOCK */
225 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
226 # define DP_ALPM_CAP (1 << 0)
228 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
229 # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
231 #define DP_GUID 0x030 /* 1.2 */
233 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
234 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
236 #define DP_DSC_REV 0x061
237 # define DP_DSC_MAJOR_MASK (0xf << 0)
238 # define DP_DSC_MINOR_MASK (0xf << 4)
239 # define DP_DSC_MAJOR_SHIFT 0
240 # define DP_DSC_MINOR_SHIFT 4
242 #define DP_DSC_RC_BUF_BLK_SIZE 0x062
243 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
244 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
245 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
246 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
248 #define DP_DSC_RC_BUF_SIZE 0x063
250 #define DP_DSC_SLICE_CAP_1 0x064
251 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
252 # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
253 # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
254 # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
255 # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
256 # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
257 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
259 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
260 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
261 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
262 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
263 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
264 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
265 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
266 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
267 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
268 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
269 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
271 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
272 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
274 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
276 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
277 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
278 # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8
280 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
281 # define DP_DSC_RGB (1 << 0)
282 # define DP_DSC_YCbCr444 (1 << 1)
283 # define DP_DSC_YCbCr422_Simple (1 << 2)
284 # define DP_DSC_YCbCr422_Native (1 << 3)
285 # define DP_DSC_YCbCr420_Native (1 << 4)
287 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
288 # define DP_DSC_8_BPC (1 << 1)
289 # define DP_DSC_10_BPC (1 << 2)
290 # define DP_DSC_12_BPC (1 << 3)
292 #define DP_DSC_PEAK_THROUGHPUT 0x06B
293 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
294 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
295 # define DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED 0
296 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
297 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
298 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
299 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
300 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
301 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
302 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
303 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
304 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
305 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
306 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
307 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
308 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
309 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
310 # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
311 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
312 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
313 # define DP_DSC_THROUGHPUT_MODE_1_UPSUPPORTED 0
314 # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
315 # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
316 # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
317 # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
318 # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
319 # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
320 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
321 # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
322 # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
323 # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
324 # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
325 # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
326 # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
327 # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
328 # define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
330 #define DP_DSC_MAX_SLICE_WIDTH 0x06C
331 #define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
332 #define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
334 #define DP_DSC_SLICE_CAP_2 0x06D
335 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
336 # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
337 # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
339 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
340 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
341 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
342 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
343 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
344 # define DP_DSC_BITS_PER_PIXEL_1 0x4
346 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
347 # define DP_PSR_IS_SUPPORTED 1
348 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
349 # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
351 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */
352 # define DP_PSR_NO_TRAIN_ON_EXIT 1
353 # define DP_PSR_SETUP_TIME_330 (0 << 1)
354 # define DP_PSR_SETUP_TIME_275 (1 << 1)
355 # define DP_PSR_SETUP_TIME_220 (2 << 1)
356 # define DP_PSR_SETUP_TIME_165 (3 << 1)
357 # define DP_PSR_SETUP_TIME_110 (4 << 1)
358 # define DP_PSR_SETUP_TIME_55 (5 << 1)
359 # define DP_PSR_SETUP_TIME_0 (6 << 1)
360 # define DP_PSR_SETUP_TIME_MASK (7 << 1)
361 # define DP_PSR_SETUP_TIME_SHIFT 1
362 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
363 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
365 #define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
366 #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
369 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
370 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
371 * each port's descriptor is one byte wide. If it was set, each port's is
372 * four bytes wide, starting with the one byte from the base info. As of
373 * DP interop v1.1a only VGA defines additional detail.
377 #define DP_DOWNSTREAM_PORT_0 0x80
378 # define DP_DS_PORT_TYPE_MASK (7 << 0)
379 # define DP_DS_PORT_TYPE_DP 0
380 # define DP_DS_PORT_TYPE_VGA 1
381 # define DP_DS_PORT_TYPE_DVI 2
382 # define DP_DS_PORT_TYPE_HDMI 3
383 # define DP_DS_PORT_TYPE_NON_EDID 4
384 # define DP_DS_PORT_TYPE_DP_DUALMODE 5
385 # define DP_DS_PORT_TYPE_WIRELESS 6
386 # define DP_DS_PORT_HPD (1 << 3)
387 /* offset 1 for VGA is maximum megapixels per second / 8 */
389 # define DP_DS_MAX_BPC_MASK (3 << 0)
390 # define DP_DS_8BPC 0
391 # define DP_DS_10BPC 1
392 # define DP_DS_12BPC 2
393 # define DP_DS_16BPC 3
395 #define DP_MAX_DOWNSTREAM_PORTS 0x10
397 /* DP Forward error Correction Registers */
398 #define DP_FEC_CAPABILITY 0x090 /* 1.4 */
399 # define DP_FEC_CAPABLE (1 << 0)
400 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
401 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
402 # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
404 /* DP Extended DSC Capabilities */
405 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
406 #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
407 #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
409 /* link configuration */
410 #define DP_LINK_BW_SET 0x100
411 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
412 # define DP_LINK_BW_1_62 0x06
413 # define DP_LINK_BW_2_7 0x0a
414 # define DP_LINK_BW_5_4 0x14 /* 1.2 */
415 # define DP_LINK_BW_8_1 0x1e /* 1.4 */
417 #define DP_LANE_COUNT_SET 0x101
418 # define DP_LANE_COUNT_MASK 0x0f
419 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
421 #define DP_TRAINING_PATTERN_SET 0x102
422 # define DP_TRAINING_PATTERN_DISABLE 0
423 # define DP_TRAINING_PATTERN_1 1
424 # define DP_TRAINING_PATTERN_2 2
425 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
426 # define DP_TRAINING_PATTERN_4 7 /* 1.4 */
427 # define DP_TRAINING_PATTERN_MASK 0x3
428 # define DP_TRAINING_PATTERN_MASK_1_4 0xf
430 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
431 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
432 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
433 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
434 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
435 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
437 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
438 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
440 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
441 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
442 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
443 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
445 #define DP_TRAINING_LANE0_SET 0x103
446 #define DP_TRAINING_LANE1_SET 0x104
447 #define DP_TRAINING_LANE2_SET 0x105
448 #define DP_TRAINING_LANE3_SET 0x106
450 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
451 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
452 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
453 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
454 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
455 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
456 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
458 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
459 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
460 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
461 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
462 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
464 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
465 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
467 #define DP_DOWNSPREAD_CTRL 0x107
468 # define DP_SPREAD_AMP_0_5 (1 << 4)
469 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
471 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
472 # define DP_SET_ANSI_8B10B (1 << 0)
474 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
475 /* bitmask as for DP_I2C_SPEED_CAP */
477 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
478 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
479 # define DP_FRAMING_CHANGE_ENABLE (1 << 1)
480 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
482 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
483 #define DP_LINK_QUAL_LANE1_SET 0x10c
484 #define DP_LINK_QUAL_LANE2_SET 0x10d
485 #define DP_LINK_QUAL_LANE3_SET 0x10e
486 # define DP_LINK_QUAL_PATTERN_DISABLE 0
487 # define DP_LINK_QUAL_PATTERN_D10_2 1
488 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
489 # define DP_LINK_QUAL_PATTERN_PRBS7 3
490 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
491 # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5
492 # define DP_LINK_QUAL_PATTERN_MASK 7
494 #define DP_TRAINING_LANE0_1_SET2 0x10f
495 #define DP_TRAINING_LANE2_3_SET2 0x110
496 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
497 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
498 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
499 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
501 #define DP_MSTM_CTRL 0x111 /* 1.2 */
502 # define DP_MST_EN (1 << 0)
503 # define DP_UP_REQ_EN (1 << 1)
504 # define DP_UPSTREAM_IS_SRC (1 << 2)
506 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */
507 #define DP_AUDIO_DELAY1 0x113
508 #define DP_AUDIO_DELAY2 0x114
510 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
511 # define DP_LINK_RATE_SET_SHIFT 0
512 # define DP_LINK_RATE_SET_MASK (7 << 0)
514 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
515 # define DP_ALPM_ENABLE (1 << 0)
516 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
518 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
519 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
520 # define DP_IRQ_HPD_ENABLE (1 << 1)
522 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
523 # define DP_PWR_NOT_NEEDED (1 << 0)
525 #define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
526 # define DP_FEC_READY (1 << 0)
527 # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
528 # define DP_FEC_ERR_COUNT_DIS (0 << 1)
529 # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
530 # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
531 # define DP_FEC_BIT_ERROR_COUNT (3 << 1)
532 # define DP_FEC_LANE_SELECT_MASK (3 << 4)
533 # define DP_FEC_LANE_0_SELECT (0 << 4)
534 # define DP_FEC_LANE_1_SELECT (1 << 4)
535 # define DP_FEC_LANE_2_SELECT (2 << 4)
536 # define DP_FEC_LANE_3_SELECT (3 << 4)
538 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
539 # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
541 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
542 # define DP_DECOMPRESSION_EN (1 << 0)
544 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
545 # define DP_PSR_ENABLE (1 << 0)
546 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
547 # define DP_PSR_CRC_VERIFICATION (1 << 2)
548 # define DP_PSR_FRAME_CAPTURE (1 << 3)
549 # define DP_PSR_SELECTIVE_UPDATE (1 << 4)
550 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5)
551 # define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */
553 #define DP_ADAPTER_CTRL 0x1a0
554 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
556 #define DP_BRANCH_DEVICE_CTRL 0x1a1
557 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
559 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
560 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
561 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
563 #define DP_SINK_COUNT 0x200
564 /* prior to 1.2 bit 7 was reserved mbz */
565 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
566 # define DP_SINK_CP_READY (1 << 6)
568 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
569 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
570 # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
571 # define DP_CP_IRQ (1 << 2)
572 # define DP_MCCS_IRQ (1 << 3)
573 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
574 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
575 # define DP_SINK_SPECIFIC_IRQ (1 << 6)
577 #define DP_LANE0_1_STATUS 0x202
578 #define DP_LANE2_3_STATUS 0x203
579 # define DP_LANE_CR_DONE (1 << 0)
580 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
581 # define DP_LANE_SYMBOL_LOCKED (1 << 2)
583 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
584 DP_LANE_CHANNEL_EQ_DONE | \
585 DP_LANE_SYMBOL_LOCKED)
587 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
589 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
590 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
591 #define DP_LINK_STATUS_UPDATED (1 << 7)
593 #define DP_SINK_STATUS 0x205
595 #define DP_RECEIVE_PORT_0_STATUS (1 << 0)
596 #define DP_RECEIVE_PORT_1_STATUS (1 << 1)
598 #define DP_ADJUST_REQUEST_LANE0_1 0x206
599 #define DP_ADJUST_REQUEST_LANE2_3 0x207
600 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
601 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
602 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
603 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
604 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
605 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
606 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
607 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
609 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
610 # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
611 # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
612 # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
613 # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
614 # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
615 # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
616 # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
617 # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
619 #define DP_TEST_REQUEST 0x218
620 # define DP_TEST_LINK_TRAINING (1 << 0)
621 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
622 # define DP_TEST_LINK_EDID_READ (1 << 2)
623 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
624 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
625 # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
626 # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
628 #define DP_TEST_LINK_RATE 0x219
629 # define DP_LINK_RATE_162 (0x6)
630 # define DP_LINK_RATE_27 (0xa)
632 #define DP_TEST_LANE_COUNT 0x220
634 #define DP_TEST_PATTERN 0x221
635 # define DP_NO_TEST_PATTERN 0x0
636 # define DP_COLOR_RAMP 0x1
637 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
638 # define DP_COLOR_SQUARE 0x3
640 #define DP_TEST_H_TOTAL_HI 0x222
641 #define DP_TEST_H_TOTAL_LO 0x223
643 #define DP_TEST_V_TOTAL_HI 0x224
644 #define DP_TEST_V_TOTAL_LO 0x225
646 #define DP_TEST_H_START_HI 0x226
647 #define DP_TEST_H_START_LO 0x227
649 #define DP_TEST_V_START_HI 0x228
650 #define DP_TEST_V_START_LO 0x229
652 #define DP_TEST_HSYNC_HI 0x22A
653 # define DP_TEST_HSYNC_POLARITY (1 << 7)
654 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
655 #define DP_TEST_HSYNC_WIDTH_LO 0x22B
657 #define DP_TEST_VSYNC_HI 0x22C
658 # define DP_TEST_VSYNC_POLARITY (1 << 7)
659 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
660 #define DP_TEST_VSYNC_WIDTH_LO 0x22D
662 #define DP_TEST_H_WIDTH_HI 0x22E
663 #define DP_TEST_H_WIDTH_LO 0x22F
665 #define DP_TEST_V_HEIGHT_HI 0x230
666 #define DP_TEST_V_HEIGHT_LO 0x231
668 #define DP_TEST_MISC0 0x232
669 # define DP_TEST_SYNC_CLOCK (1 << 0)
670 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
671 # define DP_TEST_COLOR_FORMAT_SHIFT 1
672 # define DP_COLOR_FORMAT_RGB (0 << 1)
673 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
674 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
675 # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
676 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
677 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
678 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
679 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
680 # define DP_TEST_BIT_DEPTH_MASK (7 << 5)
681 # define DP_TEST_BIT_DEPTH_SHIFT 5
682 # define DP_TEST_BIT_DEPTH_6 (0 << 5)
683 # define DP_TEST_BIT_DEPTH_8 (1 << 5)
684 # define DP_TEST_BIT_DEPTH_10 (2 << 5)
685 # define DP_TEST_BIT_DEPTH_12 (3 << 5)
686 # define DP_TEST_BIT_DEPTH_16 (4 << 5)
688 #define DP_TEST_MISC1 0x233
689 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
690 # define DP_TEST_INTERLACED (1 << 1)
692 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
694 #define DP_TEST_MISC0 0x232
696 #define DP_TEST_CRC_R_CR 0x240
697 #define DP_TEST_CRC_G_Y 0x242
698 #define DP_TEST_CRC_B_CB 0x244
700 #define DP_TEST_SINK_MISC 0x246
701 # define DP_TEST_CRC_SUPPORTED (1 << 5)
702 # define DP_TEST_COUNT_MASK 0xf
704 #define DP_TEST_PHY_PATTERN 0x248
705 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
706 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
707 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
708 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
709 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
710 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
711 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
712 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
713 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
714 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
716 #define DP_TEST_RESPONSE 0x260
717 # define DP_TEST_ACK (1 << 0)
718 # define DP_TEST_NAK (1 << 1)
719 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
721 #define DP_TEST_EDID_CHECKSUM 0x261
723 #define DP_TEST_SINK 0x270
724 # define DP_TEST_SINK_START (1 << 0)
725 #define DP_TEST_AUDIO_MODE 0x271
726 #define DP_TEST_AUDIO_PATTERN_TYPE 0x272
727 #define DP_TEST_AUDIO_PERIOD_CH1 0x273
728 #define DP_TEST_AUDIO_PERIOD_CH2 0x274
729 #define DP_TEST_AUDIO_PERIOD_CH3 0x275
730 #define DP_TEST_AUDIO_PERIOD_CH4 0x276
731 #define DP_TEST_AUDIO_PERIOD_CH5 0x277
732 #define DP_TEST_AUDIO_PERIOD_CH6 0x278
733 #define DP_TEST_AUDIO_PERIOD_CH7 0x279
734 #define DP_TEST_AUDIO_PERIOD_CH8 0x27A
736 #define DP_FEC_STATUS 0x280 /* 1.4 */
737 # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
738 # define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
740 #define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
742 #define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
743 # define DP_FEC_ERROR_COUNT_MASK 0x7F
744 # define DP_FEC_ERR_COUNT_VALID (1 << 7)
746 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
747 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
748 # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
750 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
751 /* up to ID_SLOT_63 at 0x2ff */
753 #define DP_SOURCE_OUI 0x300
754 #define DP_SINK_OUI 0x400
755 #define DP_BRANCH_OUI 0x500
756 #define DP_BRANCH_ID 0x503
757 #define DP_BRANCH_REVISION_START 0x509
758 #define DP_BRANCH_HW_REV 0x509
759 #define DP_BRANCH_SW_REV 0x50A
761 #define DP_SET_POWER 0x600
762 # define DP_SET_POWER_D0 0x1
763 # define DP_SET_POWER_D3 0x2
764 # define DP_SET_POWER_MASK 0x3
765 # define DP_SET_POWER_D3_AUX_ON 0x5
767 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
768 # define DP_EDP_11 0x00
769 # define DP_EDP_12 0x01
770 # define DP_EDP_13 0x02
771 # define DP_EDP_14 0x03
772 # define DP_EDP_14a 0x04 /* eDP 1.4a */
773 # define DP_EDP_14b 0x05 /* eDP 1.4b */
775 #define DP_EDP_GENERAL_CAP_1 0x701
776 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
777 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
778 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
779 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
780 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
781 # define DP_EDP_FRC_ENABLE_CAP (1 << 5)
782 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
783 # define DP_EDP_SET_POWER_CAP (1 << 7)
785 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
786 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
787 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
788 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
789 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
790 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
791 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
792 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
793 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
795 #define DP_EDP_GENERAL_CAP_2 0x703
796 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
798 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
799 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
800 # define DP_EDP_X_REGION_CAP_SHIFT 0
801 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
802 # define DP_EDP_Y_REGION_CAP_SHIFT 4
804 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
805 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
806 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
807 # define DP_EDP_FRC_ENABLE (1 << 2)
808 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
809 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
811 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
812 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
813 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
814 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
815 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
816 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
817 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
818 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
819 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
820 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
821 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
823 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
824 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
826 #define DP_EDP_PWMGEN_BIT_COUNT 0x724
827 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
828 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
829 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
831 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
833 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
834 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
836 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
837 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
838 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
840 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
841 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
842 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
844 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
845 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
847 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
848 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
850 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
851 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
852 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
853 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
855 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
857 # define DP_SINK_COUNT_CP_READY (1 << 6)
859 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
861 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
862 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
863 # define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
864 # define DP_CEC_IRQ (1 << 2)
866 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
868 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
869 # define DP_PSR_LINK_CRC_ERROR (1 << 0)
870 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
871 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
873 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */
874 # define DP_PSR_CAPS_CHANGE (1 << 0)
876 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
877 # define DP_PSR_SINK_INACTIVE 0
878 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
879 # define DP_PSR_SINK_ACTIVE_RFB 2
880 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
881 # define DP_PSR_SINK_ACTIVE_RESYNC 4
882 # define DP_PSR_SINK_INTERNAL_ERROR 7
883 # define DP_PSR_SINK_STATE_MASK 0x07
885 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
886 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
887 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
888 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
889 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
891 #define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
892 # define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
893 # define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
894 # define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
895 # define DP_SU_VALID (1 << 3) /* eDP 1.4 */
896 # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
897 # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
898 # define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
900 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
901 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
903 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
904 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
905 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
906 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
908 #define DP_DP13_DPCD_REV 0x2200
909 #define DP_DP13_MAX_LINK_RATE 0x2201
911 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
912 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */
913 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
914 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
915 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
916 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
917 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
918 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
919 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
921 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
922 #define DP_CEC_TUNNELING_CAPABILITY 0x3000
923 # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
924 # define DP_CEC_SNOOPING_CAPABLE (1 << 1)
925 # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
927 #define DP_CEC_TUNNELING_CONTROL 0x3001
928 # define DP_CEC_TUNNELING_ENABLE (1 << 0)
929 # define DP_CEC_SNOOPING_ENABLE (1 << 1)
931 #define DP_CEC_RX_MESSAGE_INFO 0x3002
932 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
933 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
934 # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
935 # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
936 # define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
937 # define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
939 #define DP_CEC_TX_MESSAGE_INFO 0x3003
940 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
941 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
942 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
943 # define DP_CEC_TX_RETRY_COUNT_SHIFT 4
944 # define DP_CEC_TX_MESSAGE_SEND (1 << 7)
946 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
947 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
948 # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
949 # define DP_CEC_TX_MESSAGE_SENT (1 << 4)
950 # define DP_CEC_TX_LINE_ERROR (1 << 5)
951 # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
952 # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
954 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
955 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
956 # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
957 # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
958 # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
959 # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
960 # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
961 # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
962 # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
963 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
964 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
965 # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
966 # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
967 # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
968 # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
969 # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
970 # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
971 # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
973 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
974 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
975 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
977 #define DP_AUX_HDCP_BKSV 0x68000
978 #define DP_AUX_HDCP_RI_PRIME 0x68005
979 #define DP_AUX_HDCP_AKSV 0x68007
980 #define DP_AUX_HDCP_AN 0x6800C
981 #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
982 #define DP_AUX_HDCP_BCAPS 0x68028
983 # define DP_BCAPS_REPEATER_PRESENT BIT(1)
984 # define DP_BCAPS_HDCP_CAPABLE BIT(0)
985 #define DP_AUX_HDCP_BSTATUS 0x68029
986 # define DP_BSTATUS_REAUTH_REQ BIT(3)
987 # define DP_BSTATUS_LINK_FAILURE BIT(2)
988 # define DP_BSTATUS_R0_PRIME_READY BIT(1)
989 # define DP_BSTATUS_READY BIT(0)
990 #define DP_AUX_HDCP_BINFO 0x6802A
991 #define DP_AUX_HDCP_KSV_FIFO 0x6802C
992 #define DP_AUX_HDCP_AINFO 0x6803B
994 /* DP HDCP2.2 parameter offsets in DPCD address space */
995 #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
996 #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
997 #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
998 #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
999 #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1000 #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1001 #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1002 #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1003 #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1004 #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1005 #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1006 #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1007 #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1008 #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1009 #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1010 #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1011 #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1012 #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1013 #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1014 #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1015 #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1016 #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1017 #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1018 #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1019 #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1020 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1022 /* Link Training (LT)-tunable PHY Repeaters */
1023 #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1024 #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1025 #define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1026 #define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1027 #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1028 #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1029 #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1030 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1031 #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1032 #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1033 #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1034 #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1035 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1036 #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1037 #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1038 #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1039 #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1040 #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1041 #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1042 #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1043 #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1044 #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1045 #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1046 #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1047 #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1048 #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1050 /* Repeater modes */
1051 #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1052 #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1054 /* DP HDCP message start offsets in DPCD address space */
1055 #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
1056 #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
1057 #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1058 #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1059 #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
1060 #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1061 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1062 #define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
1063 #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
1064 #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1065 #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
1066 #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
1067 #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1068 #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
1070 #define HDCP_2_2_DP_RXSTATUS_LEN 1
1071 #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1072 #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
1073 #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
1074 #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
1075 #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
1077 /* DP 1.2 Sideband message defines */
1078 /* peer device type - DP 1.2a Table 2-92 */
1079 #define DP_PEER_DEVICE_NONE 0x0
1080 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1081 #define DP_PEER_DEVICE_MST_BRANCHING 0x2
1082 #define DP_PEER_DEVICE_SST_SINK 0x3
1083 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1085 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1086 #define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1087 #define DP_LINK_ADDRESS 0x01
1088 #define DP_CONNECTION_STATUS_NOTIFY 0x02
1089 #define DP_ENUM_PATH_RESOURCES 0x10
1090 #define DP_ALLOCATE_PAYLOAD 0x11
1091 #define DP_QUERY_PAYLOAD 0x12
1092 #define DP_RESOURCE_STATUS_NOTIFY 0x13
1093 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1094 #define DP_REMOTE_DPCD_READ 0x20
1095 #define DP_REMOTE_DPCD_WRITE 0x21
1096 #define DP_REMOTE_I2C_READ 0x22
1097 #define DP_REMOTE_I2C_WRITE 0x23
1098 #define DP_POWER_UP_PHY 0x24
1099 #define DP_POWER_DOWN_PHY 0x25
1100 #define DP_SINK_EVENT_NOTIFY 0x30
1101 #define DP_QUERY_STREAM_ENC_STATUS 0x38
1103 /* DP 1.2 MST sideband reply types */
1104 #define DP_SIDEBAND_REPLY_ACK 0x00
1105 #define DP_SIDEBAND_REPLY_NAK 0x01
1107 /* DP 1.2 MST sideband nak reasons - table 2.84 */
1108 #define DP_NAK_WRITE_FAILURE 0x01
1109 #define DP_NAK_INVALID_READ 0x02
1110 #define DP_NAK_CRC_FAILURE 0x03
1111 #define DP_NAK_BAD_PARAM 0x04
1112 #define DP_NAK_DEFER 0x05
1113 #define DP_NAK_LINK_FAILURE 0x06
1114 #define DP_NAK_NO_RESOURCES 0x07
1115 #define DP_NAK_DPCD_FAIL 0x08
1116 #define DP_NAK_I2C_NAK 0x09
1117 #define DP_NAK_ALLOCATE_FAIL 0x0a
1119 #define MODE_I2C_START 1
1120 #define MODE_I2C_WRITE 2
1121 #define MODE_I2C_READ 4
1122 #define MODE_I2C_STOP 8
1124 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1125 #define DP_MST_PHYSICAL_PORT_0 0
1126 #define DP_MST_LOGICAL_PORT_0 8
1128 #define DP_LINK_STATUS_SIZE 6
1129 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1131 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
1133 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
1135 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
1137 u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
1140 #define DP_BRANCH_OUI_HEADER_SIZE 0xc
1141 #define DP_RECEIVER_CAP_SIZE 0xf
1142 #define DP_DSC_RECEIVER_CAP_SIZE 0xf
1143 #define EDP_PSR_RECEIVER_CAP_SIZE 2
1144 #define EDP_DISPLAY_CTL_CAP_SIZE 3
1146 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1147 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1149 u8 drm_dp_link_rate_to_bw_code(int link_rate);
1150 int drm_dp_bw_code_to_link_rate(u8 link_bw);
1152 #define DP_SDP_AUDIO_TIMESTAMP 0x01
1153 #define DP_SDP_AUDIO_STREAM 0x02
1154 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1155 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1156 #define DP_SDP_ISRC 0x06 /* DP 1.2 */
1157 #define DP_SDP_VSC 0x07 /* DP 1.2 */
1158 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1159 #define DP_SDP_PPS 0x10 /* DP 1.4 */
1160 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1161 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1162 /* 0x80+ CEA-861 infoframe types */
1165 * struct dp_sdp_header - DP secondary data packet header
1166 * @HB0: Secondary Data Packet ID
1167 * @HB1: Secondary Data Packet Type
1168 * @HB2: Secondary Data Packet Specific header, Byte 0
1169 * @HB3: Secondary Data packet Specific header, Byte 1
1171 struct dp_sdp_header {
1178 #define EDP_SDP_HEADER_REVISION_MASK 0x1F
1179 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1180 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1183 * struct dp_sdp - DP secondary data packet
1184 * @sdp_header: DP secondary data packet header
1185 * @db: DP secondaray data packet data blocks
1186 * VSC SDP Payload for PSR
1187 * db[0]: Stereo Interface
1188 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1189 * db[2]: CRC value bits 7:0 of the R or Cr component
1190 * db[3]: CRC value bits 15:8 of the R or Cr component
1191 * db[4]: CRC value bits 7:0 of the G or Y component
1192 * db[5]: CRC value bits 15:8 of the G or Y component
1193 * db[6]: CRC value bits 7:0 of the B or Cb component
1194 * db[7]: CRC value bits 15:8 of the B or Cb component
1195 * db[8] - db[31]: Reserved
1196 * VSC SDP Payload for Pixel Encoding/Colorimetry Format
1197 * db[0] - db[15]: Reserved
1198 * db[16]: Pixel Encoding and Colorimetry Formats
1199 * db[17]: Dynamic Range and Component Bit Depth
1200 * db[18]: Content Type
1201 * db[19] - db[31]: Reserved
1204 struct dp_sdp_header sdp_header;
1208 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1209 #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1210 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1212 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
1215 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1217 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
1221 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1223 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
1227 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1229 return dpcd[DP_DPCD_REV] >= 0x11 &&
1230 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1234 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1236 return dpcd[DP_DPCD_REV] >= 0x11 &&
1237 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
1241 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1243 return dpcd[DP_DPCD_REV] >= 0x12 &&
1244 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
1248 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1250 return dpcd[DP_DPCD_REV] >= 0x14 &&
1251 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
1255 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1257 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
1258 DP_TRAINING_PATTERN_MASK;
1262 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1264 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
1267 /* DP/eDP DSC support */
1268 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
1270 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
1271 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
1275 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1277 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
1278 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
1282 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1284 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
1285 (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
1286 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
1287 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
1291 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1293 /* Max Slicewidth = Number of Pixels * 320 */
1294 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
1295 DP_DSC_SLICE_WIDTH_MULTIPLIER;
1298 /* Forward Error Correction Support on DP 1.4 */
1300 drm_dp_sink_supports_fec(const u8 fec_capable)
1302 return fec_capable & DP_FEC_CAPABLE;
1306 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1308 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
1312 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1314 return dpcd[DP_EDP_CONFIGURATION_CAP] &
1315 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
1319 * DisplayPort AUX channel
1323 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
1324 * @address: address of the (first) register to access
1325 * @request: contains the type of transaction (see DP_AUX_* macros)
1326 * @reply: upon completion, contains the reply type of the transaction
1327 * @buffer: pointer to a transmission or reception buffer
1328 * @size: size of @buffer
1330 struct drm_dp_aux_msg {
1331 unsigned int address;
1340 struct drm_connector;
1343 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
1344 * @lock: mutex protecting this struct
1345 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1346 * @connector: the connector this CEC adapter is associated with
1347 * @unregister_work: unregister the CEC adapter
1349 struct drm_dp_aux_cec {
1351 struct cec_adapter *adap;
1352 struct drm_connector *connector;
1353 struct delayed_work unregister_work;
1357 * struct drm_dp_aux - DisplayPort AUX channel
1358 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter
1359 * @ddc: I2C adapter that can be used for I2C-over-AUX communication
1360 * @dev: pointer to struct device that is the parent for this AUX channel
1361 * @crtc: backpointer to the crtc that is currently using this AUX channel
1362 * @hw_mutex: internal mutex used for locking transfers
1363 * @crc_work: worker that captures CRCs for each frame
1364 * @crc_count: counter of captured frame CRCs
1365 * @transfer: transfers a message representing a single AUX transaction
1367 * The .dev field should be set to a pointer to the device that implements
1370 * The .name field may be used to specify the name of the I2C adapter. If set to
1371 * NULL, dev_name() of .dev will be used.
1373 * Drivers provide a hardware-specific implementation of how transactions
1374 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg
1375 * structure describing the transaction is passed into this function. Upon
1376 * success, the implementation should return the number of payload bytes
1377 * that were transferred, or a negative error-code on failure. Helpers
1378 * propagate errors from the .transfer() function, with the exception of
1379 * the -EBUSY error, which causes a transaction to be retried. On a short,
1380 * helpers will return -EPROTO to make it simpler to check for failure.
1382 * An AUX channel can also be used to transport I2C messages to a sink. A
1383 * typical application of that is to access an EDID that's present in the
1384 * sink device. The .transfer() function can also be used to execute such
1385 * transactions. The drm_dp_aux_register() function registers an I2C
1386 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers
1387 * should call drm_dp_aux_unregister() to remove the I2C adapter.
1388 * The I2C adapter uses long transfers by default; if a partial response is
1389 * received, the adapter will drop down to the size given by the partial
1390 * response for this transaction only.
1392 * Note that the aux helper code assumes that the .transfer() function
1393 * only modifies the reply field of the drm_dp_aux_msg structure. The
1394 * retry logic and i2c helpers assume this is the case.
1398 struct i2c_adapter ddc;
1400 struct drm_crtc *crtc;
1401 struct mutex hw_mutex;
1402 struct work_struct crc_work;
1404 ssize_t (*transfer)(struct drm_dp_aux *aux,
1405 struct drm_dp_aux_msg *msg);
1407 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
1409 unsigned i2c_nack_count;
1411 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
1413 unsigned i2c_defer_count;
1415 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
1417 struct drm_dp_aux_cec cec;
1419 * @is_remote: Is this AUX CH actually using sideband messaging.
1424 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
1425 void *buffer, size_t size);
1426 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
1427 void *buffer, size_t size);
1430 * drm_dp_dpcd_readb() - read a single byte from the DPCD
1431 * @aux: DisplayPort AUX channel
1432 * @offset: address of the register to read
1433 * @valuep: location where the value of the register will be stored
1435 * Returns the number of bytes transferred (1) on success, or a negative
1436 * error code on failure.
1438 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
1439 unsigned int offset, u8 *valuep)
1441 return drm_dp_dpcd_read(aux, offset, valuep, 1);
1445 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
1446 * @aux: DisplayPort AUX channel
1447 * @offset: address of the register to write
1448 * @value: value to write to the register
1450 * Returns the number of bytes transferred (1) on success, or a negative
1451 * error code on failure.
1453 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
1454 unsigned int offset, u8 value)
1456 return drm_dp_dpcd_write(aux, offset, &value, 1);
1459 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
1460 u8 status[DP_LINK_STATUS_SIZE]);
1462 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
1463 u8 real_edid_checksum);
1465 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1466 const u8 port_cap[4]);
1467 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1468 const u8 port_cap[4]);
1469 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1470 void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1471 const u8 port_cap[4], struct drm_dp_aux *aux);
1473 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
1474 void drm_dp_aux_init(struct drm_dp_aux *aux);
1475 int drm_dp_aux_register(struct drm_dp_aux *aux);
1476 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
1478 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
1479 int drm_dp_stop_crc(struct drm_dp_aux *aux);
1481 struct drm_dp_dpcd_ident {
1490 * struct drm_dp_desc - DP branch/sink device descriptor
1491 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
1492 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
1494 struct drm_dp_desc {
1495 struct drm_dp_dpcd_ident ident;
1499 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
1501 u32 drm_dp_get_edid_quirks(const struct edid *edid);
1504 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
1506 * Display Port sink and branch devices in the wild have a variety of bugs, try
1507 * to collect them here. The quirks are shared, but it's up to the drivers to
1508 * implement workarounds for them. Note that because some devices have
1509 * unreliable OUIDs, the EDID of sinks should also be checked for quirks using
1510 * drm_dp_get_edid_quirks().
1514 * @DP_DPCD_QUIRK_CONSTANT_N:
1516 * The device requires main link attributes Mvid and Nvid to be limited
1517 * to 16 bits. So will give a constant value (0x8000) for compatability.
1519 DP_DPCD_QUIRK_CONSTANT_N,
1521 * @DP_DPCD_QUIRK_NO_PSR:
1523 * The device does not support PSR even if reports that it supports or
1524 * driver still need to implement proper handling for such device.
1526 DP_DPCD_QUIRK_NO_PSR,
1528 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
1530 * The device does not set SINK_COUNT to a non-zero value.
1531 * The driver should ignore SINK_COUNT during detection.
1533 DP_DPCD_QUIRK_NO_SINK_COUNT,
1535 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
1537 * The device supports MST DSC despite not supporting Virtual DPCD.
1538 * The DSC caps can be read from the physical aux instead.
1540 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
1542 * @DP_QUIRK_FORCE_DPCD_BACKLIGHT:
1544 * The device is telling the truth when it says that it uses DPCD
1545 * backlight controls, even if the system's firmware disagrees. This
1546 * quirk should be checked against both the ident and panel EDID.
1547 * When present, the driver should honor the DPCD backlight
1548 * capabilities advertised.
1550 DP_QUIRK_FORCE_DPCD_BACKLIGHT,
1554 * drm_dp_has_quirk() - does the DP device have a specific quirk
1555 * @desc: Device decriptor filled by drm_dp_read_desc()
1556 * @edid_quirks: Optional quirk bitmask filled by drm_dp_get_edid_quirks()
1557 * @quirk: Quirk to query for
1559 * Return true if DP device identified by @desc has @quirk.
1562 drm_dp_has_quirk(const struct drm_dp_desc *desc, u32 edid_quirks,
1563 enum drm_dp_quirk quirk)
1565 return (desc->quirks | edid_quirks) & BIT(quirk);
1568 #ifdef CONFIG_DRM_DP_CEC
1569 void drm_dp_cec_irq(struct drm_dp_aux *aux);
1570 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1571 struct drm_connector *connector);
1572 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
1573 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
1574 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
1576 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
1581 drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1582 struct drm_connector *connector)
1586 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
1590 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
1591 const struct edid *edid)
1595 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
1601 #endif /* _DRM_DP_HELPER_H_ */