1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2013 - 2017 Xilinx.
5 * Configuration settings for the Xilinx Zynq CSE board.
6 * See zynq-common.h for Zynq common configs
9 #ifndef __CONFIG_ZYNQ_CSE_H
10 #define __CONFIG_ZYNQ_CSE_H
12 #define CONFIG_SKIP_LOWLEVEL_INIT
14 #include <configs/zynq-common.h>
16 /* Undef unneeded configs */
17 #undef CONFIG_EXTRA_ENV_SETTINGS
21 #undef CONFIG_SYS_CBSIZE
22 #undef CONFIG_BOOTM_VXWORKS
23 #undef CONFIG_BOOTM_LINUX
25 #define CONFIG_SYS_CBSIZE 1024
27 #undef CONFIG_SYS_INIT_RAM_ADDR
28 #undef CONFIG_SYS_INIT_RAM_SIZE
29 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
30 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
31 #undef CONFIG_SPL_BSS_START_ADDR
32 #undef CONFIG_SPL_BSS_MAX_SIZE
33 #define CONFIG_SPL_BSS_START_ADDR 0x20000
34 #define CONFIG_SPL_BSS_MAX_SIZE 0x8000
36 #endif /* __CONFIG_ZYNQ_CSE_H */