2 * (c) 2011 Graf-Syteco, Matthias Weisser
5 * Configuation settings for the zmx25 board
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
16 #define CONFIG_SYS_TEXT_BASE 0xA0000000
18 #define CONFIG_SYS_GENERIC_BOARD
20 #define CONFIG_SYS_TIMER_RATE 32768
21 #define CONFIG_SYS_TIMER_COUNTER \
22 (&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
24 #define CONFIG_MACH_TYPE MACH_TYPE_ZMX25
26 * Environment settings
28 #define CONFIG_EXTRA_ENV_SETTINGS \
29 "gs_fast_boot=setenv bootdelay 5\0" \
30 "gs_slow_boot=setenv bootdelay 10\0" \
31 "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
32 "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
33 "bootm 0x81000000; bootelf 0x81000000\0"
35 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
36 #define CONFIG_SETUP_MEMORY_TAGS
37 #define CONFIG_INITRD_TAG
38 #define CONFIG_BOARD_LATE_INIT
52 #define CONFIG_MXC_GPIO
57 #define CONFIG_MXC_UART
58 #define CONFIG_MXC_UART_BASE UART2_BASE
59 #define CONFIG_CONS_INDEX 1 /* use UART2 for console */
60 #define CONFIG_BAUDRATE 115200 /* Default baud rate */
65 #define CONFIG_FEC_MXC
66 #define CONFIG_FEC_MXC_PHYADDR 0x00
72 #define CONFIG_BOOTP_BOOTFILESIZE
73 #define CONFIG_BOOTP_BOOTPATH
74 #define CONFIG_BOOTP_GATEWAY
75 #define CONFIG_BOOTP_HOSTNAME
78 * Command line configuration.
80 #define CONFIG_CMD_CACHE
85 #define CONFIG_CMD_DHCP
86 #define CONFIG_CMD_PING
87 #define CONFIG_CMD_FAT
88 #define CONFIG_CMD_USB
90 #define CONFIG_SYS_HUSH_PARSER
96 #define CONFIG_USB_EHCI /* Enable EHCI USB support */
97 #define CONFIG_USB_EHCI_MXC
98 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
99 #define CONFIG_MXC_USB_PORT 1
100 #define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL
101 #define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
102 #define CONFIG_EHCI_IS_TDI
103 #define CONFIG_USB_STORAGE
104 #define CONFIG_DOS_PARTITION
105 #define CONFIG_SUPPORT_VFAT
106 #endif /* CONFIG_CMD_USB */
109 #define CONFIG_NR_DRAM_BANKS 1
110 #define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
111 #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
113 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
114 #define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
117 * FLASH and environment organization
119 #define CONFIG_SYS_FLASH_BASE 0xA0000000
120 #define CONFIG_SYS_MAX_FLASH_BANKS 1
121 #define CONFIG_SYS_MAX_FLASH_SECT 256
123 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
124 #define CONFIG_ENV_IS_IN_FLASH 1
125 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
126 #define CONFIG_ENV_SIZE (128 * 1024)
129 * CFI FLASH driver setup
131 #define CONFIG_SYS_FLASH_CFI
132 #define CONFIG_FLASH_CFI_DRIVER
133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */
135 #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
137 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
138 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
140 #define CONFIG_SYS_CBSIZE 256
141 #define CONFIG_SYS_MAXARGS 16
142 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
143 sizeof(CONFIG_SYS_PROMPT) + 16)
144 #define CONFIG_SYS_LONGHELP
145 #define CONFIG_CMDLINE_EDITING
147 #define CONFIG_PREBOOT ""
149 #define CONFIG_BOOTDELAY 5
152 * Size of malloc() pool
154 #define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
156 #endif /* __CONFIG_H */