include/configs/yucca.h

   1 /*
   2  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /************************************************************************
   8  * 1 january 2005       Alain Saurel <asaurel@amcc.com>
   9  * Adapted to current Das U-Boot source
  10  ***********************************************************************/
  11 /************************************************************************
  12  * yucca.h - configuration for AMCC 440SPe Ref (yucca)
  13  ***********************************************************************/
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*-----------------------------------------------------------------------
  19  * High Level Configuration Options
  20  *----------------------------------------------------------------------*/
  21 #define CONFIG_4xx                      1       /* ... PPC4xx family    */
  22 #define CONFIG_440                      1       /* ... PPC440 family    */
  23 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
  24 #define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
  25 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init  */
  26 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  27 #define EXTCLK_33_33            33333333
  28 #define EXTCLK_66_66            66666666
  29 #define EXTCLK_50               50000000
  30 #define EXTCLK_83               83333333
  31
  32 #define CONFIG_SYS_TEXT_BASE    0xfffb0000
  33
  34 /*
  35  * Include common defines/options for all AMCC eval boards
  36  */
  37 #define CONFIG_HOSTNAME         yucca
  38 #include "amcc-common.h"
  39
  40 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  41 #undef  CONFIG_SHOW_BOOT_PROGRESS
  42 #undef  CONFIG_STRESS
  43
  44 /*-----------------------------------------------------------------------
  45  * Base addresses -- Note these are effective addresses where the
  46  * actual resources get mapped (not physical addresses)
  47  *----------------------------------------------------------------------*/
  48 #define CONFIG_SYS_FLASH_BASE           0xfff00000      /* start of FLASH       */
  49 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
  50
  51 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  52 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  53 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  54
  55 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  56 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  57 #define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
  58
  59 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  60 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  61 #define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
  62 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  63 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  64 #define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
  65
  66 /* base address of inbound PCIe window */
  67 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000400000000ULL
  68
  69 /* System RAM mapped to PCI space */
  70 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
  71 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  72 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  73
  74 #define CONFIG_SYS_FPGA_BASE            0xe2000000      /* epld                 */
  75 #define CONFIG_SYS_OPER_FLASH           0xe7000000      /* SRAM - OPER Flash    */
  76
  77 /* #define CONFIG_SYS_NVRAM_BASE_ADDR 0x08000000 */
  78 /*-----------------------------------------------------------------------
  79  * Initial RAM & stack pointer (placed in internal SRAM)
  80  *----------------------------------------------------------------------*/
  81 #define CONFIG_SYS_TEMP_STACK_OCM       1
  82 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
  83 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
  84 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM */
  85
  86 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  87 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  88
  89 /*-----------------------------------------------------------------------
  90  * Serial Port
  91  *----------------------------------------------------------------------*/
  92 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  93
  94 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
  95 /* #define CONFIG_SYS_EXT_SERIAL_CLOCK  (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
  96
  97 /*-----------------------------------------------------------------------
  98  * DDR SDRAM
  99  *----------------------------------------------------------------------*/
 100 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 101 #define SPD_EEPROM_ADDRESS      {0x53, 0x52}    /* SPD i2c spd addresses*/
 102 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 103
 104 /*-----------------------------------------------------------------------
 105  * I2C
 106  *----------------------------------------------------------------------*/
 107 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 108
 109 #define IIC0_BOOTPROM_ADDR      0x50
 110 #define IIC0_ALT_BOOTPROM_ADDR  0x54
 111
 112 /* Don't probe these addrs */
 113 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
 114
 115 /* #if defined(CONFIG_CMD_EEPROM) */
 116 /* #define CONFIG_SYS_I2C_EEPROM_ADDR   0x50 */ /* I2C boot EEPROM              */
 117 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
 118 /* #endif */
 119
 120 /*-----------------------------------------------------------------------
 121  * Environment
 122  *----------------------------------------------------------------------*/
 123 /* #define CONFIG_SYS_NVRAM_SIZE        (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
 124
 125 #undef  CONFIG_ENV_IS_IN_NVRAM          /* ... not in NVRAM             */
 126 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 127 #undef  CONFIG_ENV_IS_IN_EEPROM         /* ... not in EEPROM            */
 128 #define CONFIG_ENV_OVERWRITE    1
 129
 130 /*
 131  * Default environment variables
 132  */
 133 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 134         CONFIG_AMCC_DEF_ENV                                             \
 135         CONFIG_AMCC_DEF_ENV_PPC                                         \
 136         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 137         "kernel_addr=E7F10000\0"                                        \
 138         "ramdisk_addr=E7F20000\0"                                       \
 139         "pciconfighost=1\0"                                             \
 140         "pcie_mode=RP:EP:EP\0"                                          \
 141         ""
 142
 143 /*
 144  * Commands additional to the ones defined in amcc-common.h
 145  */
 146 #define CONFIG_CMD_PCI
 147 #define CONFIG_CMD_SDRAM
 148
 149 #define CONFIG_IBM_EMAC4_V4     1
 150 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 151 #define CONFIG_HAS_ETH0
 152 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 153 #define CONFIG_PHY_RESET_DELAY  1000
 154 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 155 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 156
 157 /*-----------------------------------------------------------------------
 158  * FLASH related
 159  *----------------------------------------------------------------------*/
 160 #define CONFIG_SYS_MAX_FLASH_BANKS      3       /* number of banks              */
 161 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* sectors per device           */
 162
 163 #undef  CONFIG_SYS_FLASH_CHECKSUM
 164 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 165 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 166
 167 #define CONFIG_SYS_FLASH_ADDR0          0x5555
 168 #define CONFIG_SYS_FLASH_ADDR1          0x2aaa
 169 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned char
 170
 171 #define CONFIG_SYS_FLASH_2ND_16BIT_DEV  1       /* evb440SPe has 8 and 16bit device */
 172 #define CONFIG_SYS_FLASH_2ND_ADDR       0xe7c00000 /* evb440SPe has 8 and 16bit device*/
 173
 174 #ifdef CONFIG_ENV_IS_IN_FLASH
 175 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
 176 #define CONFIG_ENV_ADDR         0xfffa0000
 177 /* #define CONFIG_ENV_ADDR              (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
 178 #define CONFIG_ENV_SIZE         0x10000 /* Size of Environment vars     */
 179 #endif /* CONFIG_ENV_IS_IN_FLASH */
 180 /*-----------------------------------------------------------------------
 181  * PCI stuff
 182  *-----------------------------------------------------------------------
 183  */
 184 /* General PCI */
 185 #define CONFIG_PCI                      /* include pci support          */
 186 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 187 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 188 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 189 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 190
 191 /* Board-specific PCI */
 192 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 193 #undef  CONFIG_SYS_PCI_MASTER_INIT
 194
 195 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 196 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 197 /* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 198
 199 /*
 200  *  NETWORK Support (PCI):
 201  */
 202 /* Support for Intel 82557/82559/82559ER chips. */
 203 #define CONFIG_EEPRO100
 204
 205 /* FB Divisor selection */
 206 #define FPGA_FB_DIV_6           6
 207 #define FPGA_FB_DIV_10          10
 208 #define FPGA_FB_DIV_12          12
 209 #define FPGA_FB_DIV_20          20
 210
 211 /* VCO Divisor selection */
 212 #define FPGA_VCO_DIV_4          4
 213 #define FPGA_VCO_DIV_6          6
 214 #define FPGA_VCO_DIV_8          8
 215 #define FPGA_VCO_DIV_10         10
 216
 217 /*----------------------------------------------------------------------------+
 218 | FPGA registers and bit definitions
 219 +----------------------------------------------------------------------------*/
 220 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
 221 /* TLB initialization makes it correspond to logical address 0xE2000000. */
 222 /* => Done init_chip.s in bootlib */
 223 #define FPGA_REG_BASE_ADDR      0xE2000000
 224 #define FPGA_GPIO_BASE_ADDR     0xE2010000
 225 #define FPGA_INT_BASE_ADDR      0xE2020000
 226
 227 /*----------------------------------------------------------------------------+
 228 | Display
 229 +----------------------------------------------------------------------------*/
 230 #define PPC440SPE_DISPLAY       FPGA_REG_BASE_ADDR
 231
 232 #define PPC440SPE_DISPLAY_D8    (FPGA_REG_BASE_ADDR+0x06)
 233 #define PPC440SPE_DISPLAY_D4    (FPGA_REG_BASE_ADDR+0x04)
 234 #define PPC440SPE_DISPLAY_D2    (FPGA_REG_BASE_ADDR+0x02)
 235 #define PPC440SPE_DISPLAY_D1    (FPGA_REG_BASE_ADDR+0x00)
 236 /*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
 237 /*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
 238
 239 /*----------------------------------------------------------------------------+
 240 | ethernet/reset/boot Register 1
 241 +----------------------------------------------------------------------------*/
 242 #define FPGA_REG10      (FPGA_REG_BASE_ADDR+0x10)
 243
 244 #define FPGA_REG10_10MHZ_ENABLE         0x8000
 245 #define FPGA_REG10_100MHZ_ENABLE        0x4000
 246 #define FPGA_REG10_GIGABIT_ENABLE       0x2000
 247 #define FPGA_REG10_FULL_DUPLEX          0x1000  /* force Full Duplex*/
 248 #define FPGA_REG10_RESET_ETH            0x0800
 249 #define FPGA_REG10_AUTO_NEG_DIS         0x0400
 250 #define FPGA_REG10_INTP_ETH             0x0200
 251
 252 #define FPGA_REG10_RESET_HISR           0x0080
 253 #define FPGA_REG10_ENABLE_DISPLAY       0x0040
 254 #define FPGA_REG10_RESET_SDRAM          0x0020
 255 #define FPGA_REG10_OPER_BOOT            0x0010
 256 #define FPGA_REG10_SRAM_BOOT            0x0008
 257 #define FPGA_REG10_SMALL_BOOT           0x0004
 258 #define FPGA_REG10_FORCE_COLA           0x0002
 259 #define FPGA_REG10_COLA_MANUAL          0x0001
 260
 261 #define FPGA_REG10_SDRAM_ENABLE         0x0020
 262
 263 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
 264 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
 265
 266 /*----------------------------------------------------------------------------+
 267 | MUX control
 268 +----------------------------------------------------------------------------*/
 269 #define FPGA_REG12      (FPGA_REG_BASE_ADDR+0x12)
 270
 271 #define FPGA_REG12_EBC_CTL              0x8000
 272 #define FPGA_REG12_UART1_CTS_RTS        0x4000
 273 #define FPGA_REG12_UART0_RX_ENABLE      0x2000
 274 #define FPGA_REG12_UART1_RX_ENABLE      0x1000
 275 #define FPGA_REG12_UART2_RX_ENABLE      0x0800
 276 #define FPGA_REG12_EBC_OUT_ENABLE       0x0400
 277 #define FPGA_REG12_GPIO0_OUT_ENABLE     0x0200
 278 #define FPGA_REG12_GPIO1_OUT_ENABLE     0x0100
 279 #define FPGA_REG12_GPIO_SELECT          0x0010
 280 #define FPGA_REG12_GPIO_CHREG           0x0008
 281 #define FPGA_REG12_GPIO_CLK_CHREG       0x0004
 282 #define FPGA_REG12_GPIO_OETRI           0x0002
 283 #define FPGA_REG12_EBC_ERROR            0x0001
 284
 285 /*----------------------------------------------------------------------------+
 286 | PCI Clock control
 287 +----------------------------------------------------------------------------*/
 288 #define FPGA_REG16      (FPGA_REG_BASE_ADDR+0x16)
 289
 290 #define FPGA_REG16_PCI_CLK_CTL0         0x8000
 291 #define FPGA_REG16_PCI_CLK_CTL1         0x4000
 292 #define FPGA_REG16_PCI_CLK_CTL2         0x2000
 293 #define FPGA_REG16_PCI_CLK_CTL3         0x1000
 294 #define FPGA_REG16_PCI_CLK_CTL4         0x0800
 295 #define FPGA_REG16_PCI_CLK_CTL5         0x0400
 296 #define FPGA_REG16_PCI_CLK_CTL6         0x0200
 297 #define FPGA_REG16_PCI_CLK_CTL7         0x0100
 298 #define FPGA_REG16_PCI_CLK_CTL8         0x0080
 299 #define FPGA_REG16_PCI_CLK_CTL9         0x0040
 300 #define FPGA_REG16_PCI_EXT_ARB0         0x0020
 301 #define FPGA_REG16_PCI_MODE_1           0x0010
 302 #define FPGA_REG16_PCI_TARGET_MODE      0x0008
 303 #define FPGA_REG16_PCI_INTP_MODE        0x0004
 304
 305 /* FB1 Divisor selection */
 306 #define FPGA_REG16_FB2_DIV_MASK         0x1000
 307 #define FPGA_REG16_FB2_DIV_LOW          0x0000
 308 #define FPGA_REG16_FB2_DIV_HIGH         0x1000
 309 /* FB2 Divisor selection */
 310 /* S3 switch on Board */
 311 #define FPGA_REG16_FB1_DIV_MASK         0x2000
 312 #define FPGA_REG16_FB1_DIV_LOW          0x0000
 313 #define FPGA_REG16_FB1_DIV_HIGH         0x2000
 314 /* PCI0 Clock Selection */
 315 /* S3 switch on Board */
 316 #define FPGA_REG16_PCI0_CLK_MASK        0x0c00
 317 #define FPGA_REG16_PCI0_CLK_33_33       0x0000
 318 #define FPGA_REG16_PCI0_CLK_66_66       0x0800
 319 #define FPGA_REG16_PCI0_CLK_100         0x0400
 320 #define FPGA_REG16_PCI0_CLK_133_33      0x0c00
 321 /* VCO Divisor selection */
 322 /* S3 switch on Board */
 323 #define FPGA_REG16_VCO_DIV_MASK         0xc000
 324 #define FPGA_REG16_VCO_DIV_4            0x0000
 325 #define FPGA_REG16_VCO_DIV_8            0x4000
 326 #define FPGA_REG16_VCO_DIV_6            0x8000
 327 #define FPGA_REG16_VCO_DIV_10           0xc000
 328 /* Master Clock Selection */
 329 /* S3, S4 switches on Board */
 330 #define FPGA_REG16_MASTER_CLK_MASK      0x01c0
 331 #define FPGA_REG16_MASTER_CLK_EXT       0x0000
 332 #define FPGA_REG16_MASTER_CLK_66_66     0x0040
 333 #define FPGA_REG16_MASTER_CLK_50        0x0080
 334 #define FPGA_REG16_MASTER_CLK_33_33     0x00c0
 335 #define FPGA_REG16_MASTER_CLK_25        0x0100
 336
 337 /*----------------------------------------------------------------------------+
 338 | PCI Miscellaneous
 339 +----------------------------------------------------------------------------*/
 340 #define FPGA_REG18      (FPGA_REG_BASE_ADDR+0x18)
 341
 342 #define FPGA_REG18_PCI_PRSNT1           0x8000
 343 #define FPGA_REG18_PCI_PRSNT2           0x4000
 344 #define FPGA_REG18_PCI_INTA             0x2000
 345 #define FPGA_REG18_PCI_SLOT0_INTP       0x1000
 346 #define FPGA_REG18_PCI_SLOT1_INTP       0x0800
 347 #define FPGA_REG18_PCI_SLOT2_INTP       0x0400
 348 #define FPGA_REG18_PCI_SLOT3_INTP       0x0200
 349 #define FPGA_REG18_PCI_PCI0_VC          0x0100
 350 #define FPGA_REG18_PCI_PCI0_VTH1        0x0080
 351 #define FPGA_REG18_PCI_PCI0_VTH2        0x0040
 352 #define FPGA_REG18_PCI_PCI0_VTH3        0x0020
 353
 354 /*----------------------------------------------------------------------------+
 355 | PCIe Miscellaneous
 356 +----------------------------------------------------------------------------*/
 357 #define FPGA_REG1A      (FPGA_REG_BASE_ADDR+0x1A)
 358
 359 #define FPGA_REG1A_PE0_GLED             0x8000
 360 #define FPGA_REG1A_PE1_GLED             0x4000
 361 #define FPGA_REG1A_PE2_GLED             0x2000
 362 #define FPGA_REG1A_PE0_YLED             0x1000
 363 #define FPGA_REG1A_PE1_YLED             0x0800
 364 #define FPGA_REG1A_PE2_YLED             0x0400
 365 #define FPGA_REG1A_PE0_PWRON            0x0200
 366 #define FPGA_REG1A_PE1_PWRON            0x0100
 367 #define FPGA_REG1A_PE2_PWRON            0x0080
 368 #define FPGA_REG1A_PE0_REFCLK_ENABLE    0x0040
 369 #define FPGA_REG1A_PE1_REFCLK_ENABLE    0x0020
 370 #define FPGA_REG1A_PE2_REFCLK_ENABLE    0x0010
 371 #define FPGA_REG1A_PE_SPREAD0           0x0008
 372 #define FPGA_REG1A_PE_SPREAD1           0x0004
 373 #define FPGA_REG1A_PE_SELSOURCE_0       0x0002
 374 #define FPGA_REG1A_PE_SELSOURCE_1       0x0001
 375
 376 #define FPGA_REG1A_GLED_ENCODE(n)       (FPGA_REG1A_PE0_GLED >> (n))
 377 #define FPGA_REG1A_YLED_ENCODE(n)       (FPGA_REG1A_PE0_YLED >> (n))
 378 #define FPGA_REG1A_PWRON_ENCODE(n)      (FPGA_REG1A_PE0_PWRON >> (n))
 379 #define FPGA_REG1A_REFCLK_ENCODE(n)     (FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
 380
 381 /*----------------------------------------------------------------------------+
 382 | PCIe Miscellaneous
 383 +----------------------------------------------------------------------------*/
 384 #define FPGA_REG1C      (FPGA_REG_BASE_ADDR+0x1C)
 385
 386 #define FPGA_REG1C_PE0_ROOTPOINT        0x8000
 387 #define FPGA_REG1C_PE1_ENDPOINT         0x4000
 388 #define FPGA_REG1C_PE2_ENDPOINT         0x2000
 389 #define FPGA_REG1C_PE0_PRSNT            0x1000
 390 #define FPGA_REG1C_PE1_PRSNT            0x0800
 391 #define FPGA_REG1C_PE2_PRSNT            0x0400
 392 #define FPGA_REG1C_PE0_WAKE             0x0080
 393 #define FPGA_REG1C_PE1_WAKE             0x0040
 394 #define FPGA_REG1C_PE2_WAKE             0x0020
 395 #define FPGA_REG1C_PE0_PERST            0x0010
 396 #define FPGA_REG1C_PE1_PERST            0x0008
 397 #define FPGA_REG1C_PE2_PERST            0x0004
 398
 399 #define FPGA_REG1C_ROOTPOINT_ENCODE(n)  (FPGA_REG1C_PE0_ROOTPOINT >> (n))
 400 #define FPGA_REG1C_PERST_ENCODE(n)      (FPGA_REG1C_PE0_PERST >> (n))
 401
 402 /*----------------------------------------------------------------------------+
 403 | Defines
 404 +----------------------------------------------------------------------------*/
 405 #define PERIOD_133_33MHZ        7500    /* 7,5ns */
 406 #define PERIOD_100_00MHZ        10000   /* 10ns */
 407 #define PERIOD_83_33MHZ         12000   /* 12ns */
 408 #define PERIOD_75_00MHZ         13333   /* 13,333ns */
 409 #define PERIOD_66_66MHZ         15000   /* 15ns */
 410 #define PERIOD_50_00MHZ         20000   /* 20ns */
 411 #define PERIOD_33_33MHZ         30000   /* 30ns */
 412 #define PERIOD_25_00MHZ         40000   /* 40ns */
 413
 414 #endif  /* __CONFIG_H */