2 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /************************************************************************
24 * 1 january 2005 Alain Saurel <asaurel@amcc.com>
25 * Adapted to current Das U-Boot source
26 ***********************************************************************/
27 /************************************************************************
28 * yucca.h - configuration for AMCC 440SPe Ref (yucca)
29 ***********************************************************************/
34 /*-----------------------------------------------------------------------
35 * High Level Configuration Options
36 *----------------------------------------------------------------------*/
37 #define CONFIG_4xx 1 /* ... PPC4xx family */
38 #define CONFIG_440 1 /* ... PPC440 family */
39 #define CONFIG_440SPE 1 /* Specifc SPe support */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
41 #undef CFG_DRAM_TEST /* Disable-takes long time */
42 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
43 #define EXTCLK_33_33 33333333
44 #define EXTCLK_66_66 66666666
45 #define EXTCLK_50 50000000
46 #define EXTCLK_83 83333333
48 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
49 #define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
50 #undef CONFIG_SHOW_BOOT_PROGRESS
53 /*-----------------------------------------------------------------------
54 * Base addresses -- Note these are effective addresses where the
55 * actual resources get mapped (not physical addresses)
56 *----------------------------------------------------------------------*/
57 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
58 #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
59 #define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */
60 #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
61 #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
63 #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
64 #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
65 #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
67 #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
68 #define CFG_PCIE_MEMSIZE 0x01000000
69 #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
71 #define CFG_PCIE0_CFGBASE 0xc0000000
72 #define CFG_PCIE0_XCFGBASE 0xc0000400
73 #define CFG_PCIE1_CFGBASE 0xc0001000
74 #define CFG_PCIE1_XCFGBASE 0xc0001400
75 #define CFG_PCIE2_CFGBASE 0xc0002000
76 #define CFG_PCIE2_XCFGBASE 0xc0002400
78 /* System RAM mapped to PCI space */
79 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
80 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
81 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
83 #define CFG_FPGA_BASE 0xe2000000 /* epld */
84 #define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
86 /* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
87 /*-----------------------------------------------------------------------
88 * Initial RAM & stack pointer (placed in internal SRAM)
89 *----------------------------------------------------------------------*/
90 #define CFG_TEMP_STACK_OCM 1
91 #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
92 #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
93 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
94 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
96 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
97 #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
98 #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
100 #define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */
101 #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
103 /*-----------------------------------------------------------------------
105 *----------------------------------------------------------------------*/
106 #define CONFIG_SERIAL_MULTI 1
107 #undef CONFIG_UART1_CONSOLE
109 #undef CONFIG_SERIAL_SOFTWARE_FIFO
110 #undef CFG_EXT_SERIAL_CLOCK
111 /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
113 #define CONFIG_BAUDRATE 115200
115 #define CFG_BAUDRATE_TABLE \
116 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
118 /*-----------------------------------------------------------------------
120 *----------------------------------------------------------------------*/
121 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
122 #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
123 #define CONFIG_DDR_ECC 1 /* with ECC support */
125 /*-----------------------------------------------------------------------
127 *----------------------------------------------------------------------*/
128 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
129 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
130 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
131 #define CFG_I2C_SLAVE 0x7F
133 #define IIC0_BOOTPROM_ADDR 0x50
134 #define IIC0_ALT_BOOTPROM_ADDR 0x54
136 /* Don't probe these addrs */
137 #define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
139 /* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
140 /* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
141 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
144 /*-----------------------------------------------------------------------
146 *----------------------------------------------------------------------*/
147 /* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
149 #undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
150 #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
151 #undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
152 #define CONFIG_ENV_OVERWRITE 1
154 #define CONFIG_PREBOOT "echo;" \
155 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
158 #undef CONFIG_BOOTARGS
160 #define CONFIG_EXTRA_ENV_SETTINGS \
163 "nfsargs=setenv bootargs root=/dev/nfs rw " \
164 "nfsroot=${serverip}:${rootpath}\0" \
165 "ramargs=setenv bootargs root=/dev/ram rw\0" \
166 "addip=setenv bootargs ${bootargs} " \
167 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
168 ":${hostname}:${netdev}:off panic=1\0" \
169 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
170 "flash_nfs=run nfsargs addip addtty;" \
171 "bootm ${kernel_addr}\0" \
172 "flash_self=run ramargs addip addtty;" \
173 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
174 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
176 "rootpath=/opt/eldk/ppc_4xx\0" \
177 "bootfile=yucca/uImage\0" \
178 "kernel_addr=E7F10000\0" \
179 "ramdisk_addr=E7F20000\0" \
180 "initrd_high=30000000\0" \
181 "load=tftp 100000 yuca/u-boot.bin\0" \
182 "update=protect off 2:4-7;era 2:4-7;" \
183 "cp.b ${fileaddr} FFFB0000 ${filesize};" \
184 "setenv filesize;saveenv\0" \
185 "upd=run load;run update\0" \
187 #define CONFIG_BOOTCOMMAND "run flash_self"
189 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
191 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
192 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
194 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
210 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
211 #include <cmd_confdefs.h>
213 #define CONFIG_IBM_EMAC4_V4 1
214 #define CONFIG_MII 1 /* MII PHY management */
215 #undef CONFIG_NET_MULTI
216 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
217 #define CONFIG_HAS_ETH0
218 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
219 #define CONFIG_PHY_RESET_DELAY 1000
220 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
221 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
222 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
224 #define CONFIG_NETCONSOLE /* include NetConsole support */
225 #define CONFIG_NET_MULTI /* needed for NetConsole */
227 #undef CONFIG_WATCHDOG /* watchdog disabled */
230 * Miscellaneous configurable options
232 #define CFG_LONGHELP /* undef to save memory */
233 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
235 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
236 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
238 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
240 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
241 #define CFG_MAXARGS 16 /* max number of command args */
242 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
244 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
245 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
247 #define CFG_LOAD_ADDR 0x100000 /* default load address */
248 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
250 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
252 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
253 #define CONFIG_LOOPW 1 /* enable loopw command */
254 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
255 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
256 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
258 /*-----------------------------------------------------------------------
260 *----------------------------------------------------------------------*/
261 #define CFG_MAX_FLASH_BANKS 3 /* number of banks */
262 #define CFG_MAX_FLASH_SECT 256 /* sectors per device */
264 #undef CFG_FLASH_CHECKSUM
265 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
266 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
268 #define CFG_FLASH_ADDR0 0x5555
269 #define CFG_FLASH_ADDR1 0x2aaa
270 #define CFG_FLASH_WORD_SIZE unsigned char
272 #define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */
273 #define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/
275 #ifdef CFG_ENV_IS_IN_FLASH
276 #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
277 #define CFG_ENV_ADDR 0xfffa0000
278 /* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
279 #define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */
280 #endif /* CFG_ENV_IS_IN_FLASH */
281 /*-----------------------------------------------------------------------
283 *-----------------------------------------------------------------------
286 #define CONFIG_PCI /* include pci support */
287 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
288 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
289 #undef CONFIG_PCI_CONFIG_HOST_BRIDGE
291 /* Board-specific PCI */
292 #define CFG_PCI_TARGET_INIT /* let board init pci target */
293 #undef CFG_PCI_MASTER_INIT
295 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
296 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
297 /* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
300 * NETWORK Support (PCI):
302 /* Support for Intel 82557/82559/82559ER chips. */
303 #define CONFIG_EEPRO100
306 * For booting Linux, the board info and command line data
307 * have to be in the first 8 MB of memory, since this is
308 * the maximum mapped by the Linux kernel during initialization.
310 #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
311 /*-----------------------------------------------------------------------
312 * Cache Configuration
314 #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
315 #define CFG_CACHELINE_SIZE 32 /* ... */
316 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
317 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
321 * Internal Definitions
325 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
326 #define BOOTFLAG_WARM 0x02 /* Software reboot */
328 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
329 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
330 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
333 /* FB Divisor selection */
334 #define FPGA_FB_DIV_6 6
335 #define FPGA_FB_DIV_10 10
336 #define FPGA_FB_DIV_12 12
337 #define FPGA_FB_DIV_20 20
339 /* VCO Divisor selection */
340 #define FPGA_VCO_DIV_4 4
341 #define FPGA_VCO_DIV_6 6
342 #define FPGA_VCO_DIV_8 8
343 #define FPGA_VCO_DIV_10 10
345 /*----------------------------------------------------------------------------+
346 | FPGA registers and bit definitions
347 +----------------------------------------------------------------------------*/
348 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
349 /* TLB initialization makes it correspond to logical address 0xE2000000. */
350 /* => Done init_chip.s in bootlib */
351 #define FPGA_REG_BASE_ADDR 0xE2000000
352 #define FPGA_GPIO_BASE_ADDR 0xE2010000
353 #define FPGA_INT_BASE_ADDR 0xE2020000
355 /*----------------------------------------------------------------------------+
357 +----------------------------------------------------------------------------*/
358 #define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR
360 #define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06)
361 #define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04)
362 #define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02)
363 #define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00)
364 /*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
365 /*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/
367 /*----------------------------------------------------------------------------+
368 | ethernet/reset/boot Register 1
369 +----------------------------------------------------------------------------*/
370 #define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10)
372 #define FPGA_REG10_10MHZ_ENABLE 0x8000
373 #define FPGA_REG10_100MHZ_ENABLE 0x4000
374 #define FPGA_REG10_GIGABIT_ENABLE 0x2000
375 #define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/
376 #define FPGA_REG10_RESET_ETH 0x0800
377 #define FPGA_REG10_AUTO_NEG_DIS 0x0400
378 #define FPGA_REG10_INTP_ETH 0x0200
380 #define FPGA_REG10_RESET_HISR 0x0080
381 #define FPGA_REG10_ENABLE_DISPLAY 0x0040
382 #define FPGA_REG10_RESET_SDRAM 0x0020
383 #define FPGA_REG10_OPER_BOOT 0x0010
384 #define FPGA_REG10_SRAM_BOOT 0x0008
385 #define FPGA_REG10_SMALL_BOOT 0x0004
386 #define FPGA_REG10_FORCE_COLA 0x0002
387 #define FPGA_REG10_COLA_MANUAL 0x0001
389 #define FPGA_REG10_SDRAM_ENABLE 0x0020
391 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
392 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
394 /*----------------------------------------------------------------------------+
396 +----------------------------------------------------------------------------*/
397 #define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12)
399 #define FPGA_REG12_EBC_CTL 0x8000
400 #define FPGA_REG12_UART1_CTS_RTS 0x4000
401 #define FPGA_REG12_UART0_RX_ENABLE 0x2000
402 #define FPGA_REG12_UART1_RX_ENABLE 0x1000
403 #define FPGA_REG12_UART2_RX_ENABLE 0x0800
404 #define FPGA_REG12_EBC_OUT_ENABLE 0x0400
405 #define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200
406 #define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100
407 #define FPGA_REG12_GPIO_SELECT 0x0010
408 #define FPGA_REG12_GPIO_CHREG 0x0008
409 #define FPGA_REG12_GPIO_CLK_CHREG 0x0004
410 #define FPGA_REG12_GPIO_OETRI 0x0002
411 #define FPGA_REG12_EBC_ERROR 0x0001
413 /*----------------------------------------------------------------------------+
415 +----------------------------------------------------------------------------*/
416 #define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16)
418 #define FPGA_REG16_PCI_CLK_CTL0 0x8000
419 #define FPGA_REG16_PCI_CLK_CTL1 0x4000
420 #define FPGA_REG16_PCI_CLK_CTL2 0x2000
421 #define FPGA_REG16_PCI_CLK_CTL3 0x1000
422 #define FPGA_REG16_PCI_CLK_CTL4 0x0800
423 #define FPGA_REG16_PCI_CLK_CTL5 0x0400
424 #define FPGA_REG16_PCI_CLK_CTL6 0x0200
425 #define FPGA_REG16_PCI_CLK_CTL7 0x0100
426 #define FPGA_REG16_PCI_CLK_CTL8 0x0080
427 #define FPGA_REG16_PCI_CLK_CTL9 0x0040
428 #define FPGA_REG16_PCI_EXT_ARB0 0x0020
429 #define FPGA_REG16_PCI_MODE_1 0x0010
430 #define FPGA_REG16_PCI_TARGET_MODE 0x0008
431 #define FPGA_REG16_PCI_INTP_MODE 0x0004
433 /* FB1 Divisor selection */
434 #define FPGA_REG16_FB2_DIV_MASK 0x1000
435 #define FPGA_REG16_FB2_DIV_LOW 0x0000
436 #define FPGA_REG16_FB2_DIV_HIGH 0x1000
437 /* FB2 Divisor selection */
438 /* S3 switch on Board */
439 #define FPGA_REG16_FB1_DIV_MASK 0x2000
440 #define FPGA_REG16_FB1_DIV_LOW 0x0000
441 #define FPGA_REG16_FB1_DIV_HIGH 0x2000
442 /* PCI0 Clock Selection */
443 /* S3 switch on Board */
444 #define FPGA_REG16_PCI0_CLK_MASK 0x0c00
445 #define FPGA_REG16_PCI0_CLK_33_33 0x0000
446 #define FPGA_REG16_PCI0_CLK_66_66 0x0800
447 #define FPGA_REG16_PCI0_CLK_100 0x0400
448 #define FPGA_REG16_PCI0_CLK_133_33 0x0c00
449 /* VCO Divisor selection */
450 /* S3 switch on Board */
451 #define FPGA_REG16_VCO_DIV_MASK 0xc000
452 #define FPGA_REG16_VCO_DIV_4 0x0000
453 #define FPGA_REG16_VCO_DIV_8 0x4000
454 #define FPGA_REG16_VCO_DIV_6 0x8000
455 #define FPGA_REG16_VCO_DIV_10 0xc000
456 /* Master Clock Selection */
457 /* S3, S4 switches on Board */
458 #define FPGA_REG16_MASTER_CLK_MASK 0x01c0
459 #define FPGA_REG16_MASTER_CLK_EXT 0x0000
460 #define FPGA_REG16_MASTER_CLK_66_66 0x0040
461 #define FPGA_REG16_MASTER_CLK_50 0x0080
462 #define FPGA_REG16_MASTER_CLK_33_33 0x00c0
463 #define FPGA_REG16_MASTER_CLK_25 0x0100
465 /*----------------------------------------------------------------------------+
467 +----------------------------------------------------------------------------*/
468 #define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18)
470 #define FPGA_REG18_PCI_PRSNT1 0x8000
471 #define FPGA_REG18_PCI_PRSNT2 0x4000
472 #define FPGA_REG18_PCI_INTA 0x2000
473 #define FPGA_REG18_PCI_SLOT0_INTP 0x1000
474 #define FPGA_REG18_PCI_SLOT1_INTP 0x0800
475 #define FPGA_REG18_PCI_SLOT2_INTP 0x0400
476 #define FPGA_REG18_PCI_SLOT3_INTP 0x0200
477 #define FPGA_REG18_PCI_PCI0_VC 0x0100
478 #define FPGA_REG18_PCI_PCI0_VTH1 0x0080
479 #define FPGA_REG18_PCI_PCI0_VTH2 0x0040
480 #define FPGA_REG18_PCI_PCI0_VTH3 0x0020
482 /*----------------------------------------------------------------------------+
484 +----------------------------------------------------------------------------*/
485 #define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A)
487 #define FPGA_REG1A_PE0_GLED 0x8000
488 #define FPGA_REG1A_PE1_GLED 0x4000
489 #define FPGA_REG1A_PE2_GLED 0x2000
490 #define FPGA_REG1A_PE0_YLED 0x1000
491 #define FPGA_REG1A_PE1_YLED 0x0800
492 #define FPGA_REG1A_PE2_YLED 0x0400
493 #define FPGA_REG1A_PE0_PWRON 0x0200
494 #define FPGA_REG1A_PE1_PWRON 0x0100
495 #define FPGA_REG1A_PE2_PWRON 0x0080
496 #define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
497 #define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
498 #define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
499 #define FPGA_REG1A_PE_SPREAD0 0x0008
500 #define FPGA_REG1A_PE_SPREAD1 0x0004
501 #define FPGA_REG1A_PE_SELSOURCE_0 0x0002
502 #define FPGA_REG1A_PE_SELSOURCE_1 0x0001
504 /*----------------------------------------------------------------------------+
506 +----------------------------------------------------------------------------*/
507 #define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C)
509 #define FPGA_REG1C_PE0_ROOTPOINT 0x8000
510 #define FPGA_REG1C_PE1_ENDPOINT 0x4000
511 #define FPGA_REG1C_PE2_ENDPOINT 0x2000
512 #define FPGA_REG1C_PE0_PRSNT 0x1000
513 #define FPGA_REG1C_PE1_PRSNT 0x0800
514 #define FPGA_REG1C_PE2_PRSNT 0x0400
515 #define FPGA_REG1C_PE0_WAKE 0x0080
516 #define FPGA_REG1C_PE1_WAKE 0x0040
517 #define FPGA_REG1C_PE2_WAKE 0x0020
518 #define FPGA_REG1C_PE0_PERST 0x0010
519 #define FPGA_REG1C_PE1_PERST 0x0008
520 #define FPGA_REG1C_PE2_PERST 0x0004
522 /*----------------------------------------------------------------------------+
524 +----------------------------------------------------------------------------*/
525 #define PERIOD_133_33MHZ 7500 /* 7,5ns */
526 #define PERIOD_100_00MHZ 10000 /* 10ns */
527 #define PERIOD_83_33MHZ 12000 /* 12ns */
528 #define PERIOD_75_00MHZ 13333 /* 13,333ns */
529 #define PERIOD_66_66MHZ 15000 /* 15ns */
530 #define PERIOD_50_00MHZ 20000 /* 20ns */
531 #define PERIOD_33_33MHZ 30000 /* 30ns */
532 #define PERIOD_25_00MHZ 40000 /* 40ns */
534 /*---------------------------------------------------------------------------*/
536 #endif /* __CONFIG_H */