include/configs/yucca.h

   1 /*
   2  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /************************************************************************
   8  * 1 january 2005       Alain Saurel <asaurel@amcc.com>
   9  * Adapted to current Das U-Boot source
  10  ***********************************************************************/
  11 /************************************************************************
  12  * yucca.h - configuration for AMCC 440SPe Ref (yucca)
  13  ***********************************************************************/
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*-----------------------------------------------------------------------
  19  * High Level Configuration Options
  20  *----------------------------------------------------------------------*/
  21 #define CONFIG_440                      1       /* ... PPC440 family    */
  22 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
  23 #define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
  24 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  25 #define EXTCLK_33_33            33333333
  26 #define EXTCLK_66_66            66666666
  27 #define EXTCLK_50               50000000
  28 #define EXTCLK_83               83333333
  29
  30 #define CONFIG_SYS_TEXT_BASE    0xfffb0000
  31
  32 /*
  33  * Include common defines/options for all AMCC eval boards
  34  */
  35 #define CONFIG_HOSTNAME         yucca
  36 #include "amcc-common.h"
  37
  38 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  39 #undef  CONFIG_SHOW_BOOT_PROGRESS
  40 #undef  CONFIG_STRESS
  41
  42 /*-----------------------------------------------------------------------
  43  * Base addresses -- Note these are effective addresses where the
  44  * actual resources get mapped (not physical addresses)
  45  *----------------------------------------------------------------------*/
  46 #define CONFIG_SYS_FLASH_BASE           0xfff00000      /* start of FLASH       */
  47 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
  48
  49 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  50 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  51 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  52
  53 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  54 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  55 #define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
  56
  57 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  58 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  59 #define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
  60 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  61 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  62 #define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
  63
  64 /* base address of inbound PCIe window */
  65 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000400000000ULL
  66
  67 /* System RAM mapped to PCI space */
  68 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
  69 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  70 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  71
  72 #define CONFIG_SYS_FPGA_BASE            0xe2000000      /* epld                 */
  73 #define CONFIG_SYS_OPER_FLASH           0xe7000000      /* SRAM - OPER Flash    */
  74
  75 /* #define CONFIG_SYS_NVRAM_BASE_ADDR 0x08000000 */
  76 /*-----------------------------------------------------------------------
  77  * Initial RAM & stack pointer (placed in internal SRAM)
  78  *----------------------------------------------------------------------*/
  79 #define CONFIG_SYS_TEMP_STACK_OCM       1
  80 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
  81 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
  82 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000          /* Size of used area in RAM */
  83
  84 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  85 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  86
  87 /*-----------------------------------------------------------------------
  88  * Serial Port
  89  *----------------------------------------------------------------------*/
  90 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  91
  92 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
  93 /* #define CONFIG_SYS_EXT_SERIAL_CLOCK  (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
  94
  95 /*-----------------------------------------------------------------------
  96  * DDR SDRAM
  97  *----------------------------------------------------------------------*/
  98 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
  99 #define SPD_EEPROM_ADDRESS      {0x53, 0x52}    /* SPD i2c spd addresses*/
 100 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 101
 102 /*-----------------------------------------------------------------------
 103  * I2C
 104  *----------------------------------------------------------------------*/
 105 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 106
 107 #define IIC0_BOOTPROM_ADDR      0x50
 108 #define IIC0_ALT_BOOTPROM_ADDR  0x54
 109
 110 /* Don't probe these addrs */
 111 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
 112
 113 /* #if defined(CONFIG_CMD_EEPROM) */
 114 /* #define CONFIG_SYS_I2C_EEPROM_ADDR   0x50 */ /* I2C boot EEPROM              */
 115 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address             */
 116 /* #endif */
 117
 118 /*-----------------------------------------------------------------------
 119  * Environment
 120  *----------------------------------------------------------------------*/
 121 /* #define CONFIG_SYS_NVRAM_SIZE        (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
 122
 123 #undef  CONFIG_ENV_IS_IN_NVRAM          /* ... not in NVRAM             */
 124 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 125 #undef  CONFIG_ENV_IS_IN_EEPROM         /* ... not in EEPROM            */
 126 #define CONFIG_ENV_OVERWRITE    1
 127
 128 /*
 129  * Default environment variables
 130  */
 131 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 132         CONFIG_AMCC_DEF_ENV                                             \
 133         CONFIG_AMCC_DEF_ENV_PPC                                         \
 134         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 135         "kernel_addr=E7F10000\0"                                        \
 136         "ramdisk_addr=E7F20000\0"                                       \
 137         "pciconfighost=1\0"                                             \
 138         "pcie_mode=RP:EP:EP\0"                                          \
 139         ""
 140
 141 /*
 142  * Commands additional to the ones defined in amcc-common.h
 143  */
 144 #define CONFIG_CMD_PCI
 145 #define CONFIG_CMD_SDRAM
 146
 147 #define CONFIG_IBM_EMAC4_V4     1
 148 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 149 #define CONFIG_HAS_ETH0
 150 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 151 #define CONFIG_PHY_RESET_DELAY  1000
 152 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 153 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 154
 155 /*-----------------------------------------------------------------------
 156  * FLASH related
 157  *----------------------------------------------------------------------*/
 158 #define CONFIG_SYS_MAX_FLASH_BANKS      3       /* number of banks              */
 159 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* sectors per device           */
 160
 161 #undef  CONFIG_SYS_FLASH_CHECKSUM
 162 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 163 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 164
 165 #define CONFIG_SYS_FLASH_ADDR0          0x5555
 166 #define CONFIG_SYS_FLASH_ADDR1          0x2aaa
 167 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned char
 168
 169 #define CONFIG_SYS_FLASH_2ND_16BIT_DEV  1       /* evb440SPe has 8 and 16bit device */
 170 #define CONFIG_SYS_FLASH_2ND_ADDR       0xe7c00000 /* evb440SPe has 8 and 16bit device*/
 171
 172 #ifdef CONFIG_ENV_IS_IN_FLASH
 173 #define CONFIG_ENV_SECT_SIZE    0x10000 /* size of one complete sector  */
 174 #define CONFIG_ENV_ADDR         0xfffa0000
 175 /* #define CONFIG_ENV_ADDR              (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) */
 176 #define CONFIG_ENV_SIZE         0x10000 /* Size of Environment vars     */
 177 #endif /* CONFIG_ENV_IS_IN_FLASH */
 178 /*-----------------------------------------------------------------------
 179  * PCI stuff
 180  *-----------------------------------------------------------------------
 181  */
 182 /* General PCI */
 183 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 184 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 185 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 186
 187 /* Board-specific PCI */
 188 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 189 #undef  CONFIG_SYS_PCI_MASTER_INIT
 190
 191 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 192 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 193 /* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 194
 195 /*
 196  *  NETWORK Support (PCI):
 197  */
 198 /* Support for Intel 82557/82559/82559ER chips. */
 199 #define CONFIG_EEPRO100
 200
 201 /* FB Divisor selection */
 202 #define FPGA_FB_DIV_6           6
 203 #define FPGA_FB_DIV_10          10
 204 #define FPGA_FB_DIV_12          12
 205 #define FPGA_FB_DIV_20          20
 206
 207 /* VCO Divisor selection */
 208 #define FPGA_VCO_DIV_4          4
 209 #define FPGA_VCO_DIV_6          6
 210 #define FPGA_VCO_DIV_8          8
 211 #define FPGA_VCO_DIV_10         10
 212
 213 /*----------------------------------------------------------------------------+
 214 | FPGA registers and bit definitions
 215 +----------------------------------------------------------------------------*/
 216 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
 217 /* TLB initialization makes it correspond to logical address 0xE2000000. */
 218 /* => Done init_chip.s in bootlib */
 219 #define FPGA_REG_BASE_ADDR      0xE2000000
 220 #define FPGA_GPIO_BASE_ADDR     0xE2010000
 221 #define FPGA_INT_BASE_ADDR      0xE2020000
 222
 223 /*----------------------------------------------------------------------------+
 224 | Display
 225 +----------------------------------------------------------------------------*/
 226 #define PPC440SPE_DISPLAY       FPGA_REG_BASE_ADDR
 227
 228 #define PPC440SPE_DISPLAY_D8    (FPGA_REG_BASE_ADDR+0x06)
 229 #define PPC440SPE_DISPLAY_D4    (FPGA_REG_BASE_ADDR+0x04)
 230 #define PPC440SPE_DISPLAY_D2    (FPGA_REG_BASE_ADDR+0x02)
 231 #define PPC440SPE_DISPLAY_D1    (FPGA_REG_BASE_ADDR+0x00)
 232 /*define   WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
 233 /*#define   IOREG8(addr) *((volatile unsigned char *)(addr))*/
 234
 235 /*----------------------------------------------------------------------------+
 236 | ethernet/reset/boot Register 1
 237 +----------------------------------------------------------------------------*/
 238 #define FPGA_REG10      (FPGA_REG_BASE_ADDR+0x10)
 239
 240 #define FPGA_REG10_10MHZ_ENABLE         0x8000
 241 #define FPGA_REG10_100MHZ_ENABLE        0x4000
 242 #define FPGA_REG10_GIGABIT_ENABLE       0x2000
 243 #define FPGA_REG10_FULL_DUPLEX          0x1000  /* force Full Duplex*/
 244 #define FPGA_REG10_RESET_ETH            0x0800
 245 #define FPGA_REG10_AUTO_NEG_DIS         0x0400
 246 #define FPGA_REG10_INTP_ETH             0x0200
 247
 248 #define FPGA_REG10_RESET_HISR           0x0080
 249 #define FPGA_REG10_ENABLE_DISPLAY       0x0040
 250 #define FPGA_REG10_RESET_SDRAM          0x0020
 251 #define FPGA_REG10_OPER_BOOT            0x0010
 252 #define FPGA_REG10_SRAM_BOOT            0x0008
 253 #define FPGA_REG10_SMALL_BOOT           0x0004
 254 #define FPGA_REG10_FORCE_COLA           0x0002
 255 #define FPGA_REG10_COLA_MANUAL          0x0001
 256
 257 #define FPGA_REG10_SDRAM_ENABLE         0x0020
 258
 259 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
 260 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
 261
 262 /*----------------------------------------------------------------------------+
 263 | MUX control
 264 +----------------------------------------------------------------------------*/
 265 #define FPGA_REG12      (FPGA_REG_BASE_ADDR+0x12)
 266
 267 #define FPGA_REG12_EBC_CTL              0x8000
 268 #define FPGA_REG12_UART1_CTS_RTS        0x4000
 269 #define FPGA_REG12_UART0_RX_ENABLE      0x2000
 270 #define FPGA_REG12_UART1_RX_ENABLE      0x1000
 271 #define FPGA_REG12_UART2_RX_ENABLE      0x0800
 272 #define FPGA_REG12_EBC_OUT_ENABLE       0x0400
 273 #define FPGA_REG12_GPIO0_OUT_ENABLE     0x0200
 274 #define FPGA_REG12_GPIO1_OUT_ENABLE     0x0100
 275 #define FPGA_REG12_GPIO_SELECT          0x0010
 276 #define FPGA_REG12_GPIO_CHREG           0x0008
 277 #define FPGA_REG12_GPIO_CLK_CHREG       0x0004
 278 #define FPGA_REG12_GPIO_OETRI           0x0002
 279 #define FPGA_REG12_EBC_ERROR            0x0001
 280
 281 /*----------------------------------------------------------------------------+
 282 | PCI Clock control
 283 +----------------------------------------------------------------------------*/
 284 #define FPGA_REG16      (FPGA_REG_BASE_ADDR+0x16)
 285
 286 #define FPGA_REG16_PCI_CLK_CTL0         0x8000
 287 #define FPGA_REG16_PCI_CLK_CTL1         0x4000
 288 #define FPGA_REG16_PCI_CLK_CTL2         0x2000
 289 #define FPGA_REG16_PCI_CLK_CTL3         0x1000
 290 #define FPGA_REG16_PCI_CLK_CTL4         0x0800
 291 #define FPGA_REG16_PCI_CLK_CTL5         0x0400
 292 #define FPGA_REG16_PCI_CLK_CTL6         0x0200
 293 #define FPGA_REG16_PCI_CLK_CTL7         0x0100
 294 #define FPGA_REG16_PCI_CLK_CTL8         0x0080
 295 #define FPGA_REG16_PCI_CLK_CTL9         0x0040
 296 #define FPGA_REG16_PCI_EXT_ARB0         0x0020
 297 #define FPGA_REG16_PCI_MODE_1           0x0010
 298 #define FPGA_REG16_PCI_TARGET_MODE      0x0008
 299 #define FPGA_REG16_PCI_INTP_MODE        0x0004
 300
 301 /* FB1 Divisor selection */
 302 #define FPGA_REG16_FB2_DIV_MASK         0x1000
 303 #define FPGA_REG16_FB2_DIV_LOW          0x0000
 304 #define FPGA_REG16_FB2_DIV_HIGH         0x1000
 305 /* FB2 Divisor selection */
 306 /* S3 switch on Board */
 307 #define FPGA_REG16_FB1_DIV_MASK         0x2000
 308 #define FPGA_REG16_FB1_DIV_LOW          0x0000
 309 #define FPGA_REG16_FB1_DIV_HIGH         0x2000
 310 /* PCI0 Clock Selection */
 311 /* S3 switch on Board */
 312 #define FPGA_REG16_PCI0_CLK_MASK        0x0c00
 313 #define FPGA_REG16_PCI0_CLK_33_33       0x0000
 314 #define FPGA_REG16_PCI0_CLK_66_66       0x0800
 315 #define FPGA_REG16_PCI0_CLK_100         0x0400
 316 #define FPGA_REG16_PCI0_CLK_133_33      0x0c00
 317 /* VCO Divisor selection */
 318 /* S3 switch on Board */
 319 #define FPGA_REG16_VCO_DIV_MASK         0xc000
 320 #define FPGA_REG16_VCO_DIV_4            0x0000
 321 #define FPGA_REG16_VCO_DIV_8            0x4000
 322 #define FPGA_REG16_VCO_DIV_6            0x8000
 323 #define FPGA_REG16_VCO_DIV_10           0xc000
 324 /* Master Clock Selection */
 325 /* S3, S4 switches on Board */
 326 #define FPGA_REG16_MASTER_CLK_MASK      0x01c0
 327 #define FPGA_REG16_MASTER_CLK_EXT       0x0000
 328 #define FPGA_REG16_MASTER_CLK_66_66     0x0040
 329 #define FPGA_REG16_MASTER_CLK_50        0x0080
 330 #define FPGA_REG16_MASTER_CLK_33_33     0x00c0
 331 #define FPGA_REG16_MASTER_CLK_25        0x0100
 332
 333 /*----------------------------------------------------------------------------+
 334 | PCI Miscellaneous
 335 +----------------------------------------------------------------------------*/
 336 #define FPGA_REG18      (FPGA_REG_BASE_ADDR+0x18)
 337
 338 #define FPGA_REG18_PCI_PRSNT1           0x8000
 339 #define FPGA_REG18_PCI_PRSNT2           0x4000
 340 #define FPGA_REG18_PCI_INTA             0x2000
 341 #define FPGA_REG18_PCI_SLOT0_INTP       0x1000
 342 #define FPGA_REG18_PCI_SLOT1_INTP       0x0800
 343 #define FPGA_REG18_PCI_SLOT2_INTP       0x0400
 344 #define FPGA_REG18_PCI_SLOT3_INTP       0x0200
 345 #define FPGA_REG18_PCI_PCI0_VC          0x0100
 346 #define FPGA_REG18_PCI_PCI0_VTH1        0x0080
 347 #define FPGA_REG18_PCI_PCI0_VTH2        0x0040
 348 #define FPGA_REG18_PCI_PCI0_VTH3        0x0020
 349
 350 /*----------------------------------------------------------------------------+
 351 | PCIe Miscellaneous
 352 +----------------------------------------------------------------------------*/
 353 #define FPGA_REG1A      (FPGA_REG_BASE_ADDR+0x1A)
 354
 355 #define FPGA_REG1A_PE0_GLED             0x8000
 356 #define FPGA_REG1A_PE1_GLED             0x4000
 357 #define FPGA_REG1A_PE2_GLED             0x2000
 358 #define FPGA_REG1A_PE0_YLED             0x1000
 359 #define FPGA_REG1A_PE1_YLED             0x0800
 360 #define FPGA_REG1A_PE2_YLED             0x0400
 361 #define FPGA_REG1A_PE0_PWRON            0x0200
 362 #define FPGA_REG1A_PE1_PWRON            0x0100
 363 #define FPGA_REG1A_PE2_PWRON            0x0080
 364 #define FPGA_REG1A_PE0_REFCLK_ENABLE    0x0040
 365 #define FPGA_REG1A_PE1_REFCLK_ENABLE    0x0020
 366 #define FPGA_REG1A_PE2_REFCLK_ENABLE    0x0010
 367 #define FPGA_REG1A_PE_SPREAD0           0x0008
 368 #define FPGA_REG1A_PE_SPREAD1           0x0004
 369 #define FPGA_REG1A_PE_SELSOURCE_0       0x0002
 370 #define FPGA_REG1A_PE_SELSOURCE_1       0x0001
 371
 372 #define FPGA_REG1A_GLED_ENCODE(n)       (FPGA_REG1A_PE0_GLED >> (n))
 373 #define FPGA_REG1A_YLED_ENCODE(n)       (FPGA_REG1A_PE0_YLED >> (n))
 374 #define FPGA_REG1A_PWRON_ENCODE(n)      (FPGA_REG1A_PE0_PWRON >> (n))
 375 #define FPGA_REG1A_REFCLK_ENCODE(n)     (FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
 376
 377 /*----------------------------------------------------------------------------+
 378 | PCIe Miscellaneous
 379 +----------------------------------------------------------------------------*/
 380 #define FPGA_REG1C      (FPGA_REG_BASE_ADDR+0x1C)
 381
 382 #define FPGA_REG1C_PE0_ROOTPOINT        0x8000
 383 #define FPGA_REG1C_PE1_ENDPOINT         0x4000
 384 #define FPGA_REG1C_PE2_ENDPOINT         0x2000
 385 #define FPGA_REG1C_PE0_PRSNT            0x1000
 386 #define FPGA_REG1C_PE1_PRSNT            0x0800
 387 #define FPGA_REG1C_PE2_PRSNT            0x0400
 388 #define FPGA_REG1C_PE0_WAKE             0x0080
 389 #define FPGA_REG1C_PE1_WAKE             0x0040
 390 #define FPGA_REG1C_PE2_WAKE             0x0020
 391 #define FPGA_REG1C_PE0_PERST            0x0010
 392 #define FPGA_REG1C_PE1_PERST            0x0008
 393 #define FPGA_REG1C_PE2_PERST            0x0004
 394
 395 #define FPGA_REG1C_ROOTPOINT_ENCODE(n)  (FPGA_REG1C_PE0_ROOTPOINT >> (n))
 396 #define FPGA_REG1C_PERST_ENCODE(n)      (FPGA_REG1C_PE0_PERST >> (n))
 397
 398 /*----------------------------------------------------------------------------+
 399 | Defines
 400 +----------------------------------------------------------------------------*/
 401 #define PERIOD_133_33MHZ        7500    /* 7,5ns */
 402 #define PERIOD_100_00MHZ        10000   /* 10ns */
 403 #define PERIOD_83_33MHZ         12000   /* 12ns */
 404 #define PERIOD_75_00MHZ         13333   /* 13,333ns */
 405 #define PERIOD_66_66MHZ         15000   /* 15ns */
 406 #define PERIOD_50_00MHZ         20000   /* 20ns */
 407 #define PERIOD_33_33MHZ         30000   /* 30ns */
 408 #define PERIOD_25_00MHZ         40000   /* 40ns */
 409
 410 #endif  /* __CONFIG_H */