1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007-2013 Tensilica, Inc.
4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
10 #include <asm/arch/core.h>
11 #include <asm/addrspace.h>
12 #include <asm/config.h>
15 * The 'xtfpga' board describes a set of very similar boards with only minimal
19 /*=====================*/
20 /* Board and Processor */
21 /*=====================*/
25 /* FPGA CPU freq after init */
27 unsigned long get_board_sys_clk(void);
29 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
31 /*===================*/
33 /*===================*/
35 #if XCHAL_HAVE_PTP_MMU
36 #define CONFIG_SYS_MEMORY_BASE \
37 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
38 #define CONFIG_SYS_IO_BASE 0xf0000000
40 #define CONFIG_SYS_MEMORY_BASE 0x60000000
41 #define CONFIG_SYS_IO_BASE 0x90000000
42 #define CONFIG_MAX_MEM_MAPPED 0x10000000
47 * LX60 0x04000000 64 MB
48 * LX110 0x03000000 48 MB
49 * LX200 0x06000000 96 MB
50 * ML605 0x18000000 384 MB
51 * KC705 0x38000000 896 MB
53 * noMMU configurations can only see first 256MB of onboard memory.
56 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
57 #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
59 #define CONFIG_SYS_SDRAM_SIZE 0x10000000
62 #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
64 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
65 #ifdef CONFIG_XTFPGA_LX60
66 # define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */
68 # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
71 /* Linux boot param area in RAM (used only when booting linux) */
72 #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10)
74 /* Memory test is destructive so default must not overlap vectors or U-Boot*/
76 /* Load address for stand-alone applications.
77 * MEMADDR cannot be used here, because the definition needs to be
78 * a plain number as it's used as -Ttext argument for ld in standalone
80 * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually.
82 #if XCHAL_HAVE_PTP_MMU
83 #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
84 #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000
86 #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000
89 #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000
92 #if defined(CONFIG_MAX_MEM_MAPPED) && \
93 CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
94 #define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED
96 #define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE
99 #define XTENSA_SYS_TEXT_ADDR \
100 (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN)
102 /*==============================*/
103 /* U-Boot general configuration */
104 /*==============================*/
106 #define CONFIG_BOARD_POSTCLK_INIT
108 #define CONFIG_BOOTFILE "uImage"
109 /* Console I/O Buffer Size */
110 #define CONFIG_SYS_CBSIZE 1024
111 /* Boot Argument Buffer Size */
112 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
114 /*==============================*/
115 /* U-Boot autoboot configuration */
116 /*==============================*/
119 /*=========================================*/
120 /* FPGA Registers (board info and control) */
121 /*=========================================*/
124 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier
125 * releases may not provide any/all of these registers or at these offsets.
126 * Some of the FPGA registers are broken down into bitfields described by
127 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
130 /* Date of FPGA bitstream build in binary coded decimal (BCD) */
131 #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000)
132 #define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */
133 #define FPGAREG_MTH_WIDTH 8
134 #define FPGAREG_MTH_MASK 0xFF000000
135 #define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */
136 #define FPGAREG_DAY_WIDTH 8
137 #define FPGAREG_DAY_MASK 0x00FF0000
138 #define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/
139 #define FPGAREG_YEAR_WIDTH 16
140 #define FPGAREG_YEAR_MASK 0x0000FFFF
142 /* FPGA core clock frequency in Hz (also input to UART) */
143 #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
146 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
147 * Bits 0..5 set the lower 6 bits of the default ethernet MAC.
148 * Bit 6 is reserved for future use by Tensilica.
149 * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
150 * the base of flash * (when on/1) or to the base of RAM (when off/0).
152 #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
153 #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
154 #define FPGAREG_MAC_WIDTH 6
155 #define FPGAREG_MAC_MASK 0x3f
156 #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */
157 #define FPGAREG_BOOT_WIDTH 1
158 #define FPGAREG_BOOT_MASK 0x80
159 #define FPGAREG_BOOT_RAM 0
160 #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
162 /* Force hard reset of board by writing a code to this register */
163 #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
164 #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
166 /*====================*/
167 /* Serial Driver Info */
168 /*====================*/
170 #define CONFIG_SYS_NS16550_SERIAL
171 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
172 #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
174 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
175 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_CLK_FREQ
177 /*======================*/
178 /* Ethernet Driver Info */
179 /*======================*/
181 #define CONFIG_ETHBASE 00:50:C2:13:6f:00
182 #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000)
183 #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
185 /*=====================*/
186 /* Flash & Environment */
187 /*=====================*/
189 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
190 #define CONFIG_SYS_MAX_FLASH_BANKS 1
191 #ifdef CONFIG_XTFPGA_LX60
192 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
193 # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */
194 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
195 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
196 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
197 #elif defined(CONFIG_XTFPGA_KC705)
198 # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
199 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
200 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
201 # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000)
202 # define CONFIG_SYS_MONITOR_BASE IOADDR(0x06000000)
204 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
205 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
206 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
207 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
208 # define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
210 #define CONFIG_SYS_MAX_FLASH_SECT \
211 (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
212 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
215 * Put environment in top block (64kB)
216 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB
219 /* print 'E' for empty sector on flinfo */
220 #define CONFIG_SYS_FLASH_EMPTY_INFO
222 #endif /* __CONFIG_H */