1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007-2013 Tensilica, Inc.
4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
10 #include <asm/arch/core.h>
11 #include <asm/addrspace.h>
12 #include <asm/config.h>
15 * The 'xtfpga' board describes a set of very similar boards with only minimal
19 /*===================*/
21 /*===================*/
23 #if XCHAL_HAVE_PTP_MMU
24 #define CFG_SYS_MEMORY_BASE \
25 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
26 #define CFG_SYS_IO_BASE 0xf0000000
28 #define CFG_SYS_MEMORY_BASE 0x60000000
29 #define CFG_SYS_IO_BASE 0x90000000
30 #define CONFIG_MAX_MEM_MAPPED 0x10000000
35 * LX60 0x04000000 64 MB
36 * LX110 0x03000000 48 MB
37 * LX200 0x06000000 96 MB
38 * ML605 0x18000000 384 MB
39 * KC705 0x38000000 896 MB
41 * noMMU configurations can only see first 256MB of onboard memory.
44 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
45 #define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
47 #define CFG_SYS_SDRAM_SIZE 0x10000000
50 #define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000)
52 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
54 /* Memory test is destructive so default must not overlap vectors or U-Boot*/
56 #if defined(CONFIG_MAX_MEM_MAPPED) && \
57 CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE
58 #define XTENSA_SYS_TEXT_ADDR \
59 (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
61 #define XTENSA_SYS_TEXT_ADDR \
62 (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
65 /*==============================*/
66 /* U-Boot general configuration */
67 /*==============================*/
69 /* Console I/O Buffer Size */
70 /*==============================*/
71 /* U-Boot autoboot configuration */
72 /*==============================*/
75 /*=========================================*/
76 /* FPGA Registers (board info and control) */
77 /*=========================================*/
80 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier
81 * releases may not provide any/all of these registers or at these offsets.
82 * Some of the FPGA registers are broken down into bitfields described by
83 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
86 /* FPGA core clock frequency in Hz (also input to UART) */
87 #define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
90 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
91 * Bits 0..5 set the lower 6 bits of the default ethernet MAC.
92 * Bit 6 is reserved for future use by Tensilica.
93 * Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to
94 * the base of flash * (when on/1) or to the base of RAM (when off/0).
96 #define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
97 #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
98 #define FPGAREG_MAC_WIDTH 6
99 #define FPGAREG_MAC_MASK 0x3f
100 #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */
101 #define FPGAREG_BOOT_WIDTH 1
102 #define FPGAREG_BOOT_MASK 0x80
103 #define FPGAREG_BOOT_RAM 0
104 #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
106 /* Force hard reset of board by writing a code to this register */
107 #define CFG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
108 #define CFG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
110 /*====================*/
111 /* Serial Driver Info */
112 /*====================*/
114 #define CFG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
116 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
117 #define CFG_SYS_NS16550_CLK get_board_sys_clk()
119 /*======================*/
120 /* Ethernet Driver Info */
121 /*======================*/
123 #define CONFIG_ETHBASE 00:50:C2:13:6f:00
124 #define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000)
125 #define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
127 /*=====================*/
128 /* Flash & Environment */
129 /*=====================*/
131 #ifdef CONFIG_XTFPGA_LX60
132 # define CFG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
133 # define CFG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
134 # define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
135 #elif defined(CONFIG_XTFPGA_KC705)
136 # define CFG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
137 # define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
138 # define CFG_SYS_FLASH_BASE IOADDR(0x00000000)
140 # define CFG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
141 # define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
142 # define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
146 * Put environment in top block (64kB)
147 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB
150 /* print 'E' for empty sector on flinfo */
152 #endif /* __CONFIG_H */