1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007-2013 Tensilica, Inc.
4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
10 #include <asm/arch/core.h>
11 #include <asm/addrspace.h>
12 #include <asm/config.h>
15 * The 'xtfpga' board describes a set of very similar boards with only minimal
19 /*=====================*/
20 /* Board and Processor */
21 /*=====================*/
25 /*===================*/
27 /*===================*/
29 #if XCHAL_HAVE_PTP_MMU
30 #define CONFIG_SYS_MEMORY_BASE \
31 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
32 #define CONFIG_SYS_IO_BASE 0xf0000000
34 #define CONFIG_SYS_MEMORY_BASE 0x60000000
35 #define CONFIG_SYS_IO_BASE 0x90000000
36 #define CONFIG_MAX_MEM_MAPPED 0x10000000
41 * LX60 0x04000000 64 MB
42 * LX110 0x03000000 48 MB
43 * LX200 0x06000000 96 MB
44 * ML605 0x18000000 384 MB
45 * KC705 0x38000000 896 MB
47 * noMMU configurations can only see first 256MB of onboard memory.
50 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
51 #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
53 #define CONFIG_SYS_SDRAM_SIZE 0x10000000
56 #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
58 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
59 #ifdef CONFIG_XTFPGA_LX60
60 # define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */
62 # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
65 /* Linux boot param area in RAM (used only when booting linux) */
66 #define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10)
68 /* Memory test is destructive so default must not overlap vectors or U-Boot*/
70 /* Load address for stand-alone applications.
71 * MEMADDR cannot be used here, because the definition needs to be
72 * a plain number as it's used as -Ttext argument for ld in standalone
74 * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually.
76 #if XCHAL_HAVE_PTP_MMU
77 #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
78 #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000
80 #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000
83 #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000
86 #if defined(CONFIG_MAX_MEM_MAPPED) && \
87 CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
88 #define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED
90 #define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE
93 #define XTENSA_SYS_TEXT_ADDR \
94 (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN)
96 /*==============================*/
97 /* U-Boot general configuration */
98 /*==============================*/
100 /* Console I/O Buffer Size */
101 #define CONFIG_SYS_CBSIZE 1024
102 /* Boot Argument Buffer Size */
103 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
105 /*==============================*/
106 /* U-Boot autoboot configuration */
107 /*==============================*/
110 /*=========================================*/
111 /* FPGA Registers (board info and control) */
112 /*=========================================*/
115 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier
116 * releases may not provide any/all of these registers or at these offsets.
117 * Some of the FPGA registers are broken down into bitfields described by
118 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
121 /* Date of FPGA bitstream build in binary coded decimal (BCD) */
122 #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000)
123 #define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */
124 #define FPGAREG_MTH_WIDTH 8
125 #define FPGAREG_MTH_MASK 0xFF000000
126 #define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */
127 #define FPGAREG_DAY_WIDTH 8
128 #define FPGAREG_DAY_MASK 0x00FF0000
129 #define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/
130 #define FPGAREG_YEAR_WIDTH 16
131 #define FPGAREG_YEAR_MASK 0x0000FFFF
133 /* FPGA core clock frequency in Hz (also input to UART) */
134 #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
137 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
138 * Bits 0..5 set the lower 6 bits of the default ethernet MAC.
139 * Bit 6 is reserved for future use by Tensilica.
140 * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
141 * the base of flash * (when on/1) or to the base of RAM (when off/0).
143 #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
144 #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
145 #define FPGAREG_MAC_WIDTH 6
146 #define FPGAREG_MAC_MASK 0x3f
147 #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */
148 #define FPGAREG_BOOT_WIDTH 1
149 #define FPGAREG_BOOT_MASK 0x80
150 #define FPGAREG_BOOT_RAM 0
151 #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
153 /* Force hard reset of board by writing a code to this register */
154 #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
155 #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
157 /*====================*/
158 /* Serial Driver Info */
159 /*====================*/
161 #define CONFIG_SYS_NS16550_SERIAL
162 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
163 #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
165 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
166 #define CONFIG_SYS_NS16550_CLK get_board_sys_clk()
168 /*======================*/
169 /* Ethernet Driver Info */
170 /*======================*/
172 #define CONFIG_ETHBASE 00:50:C2:13:6f:00
173 #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000)
174 #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
176 /*=====================*/
177 /* Flash & Environment */
178 /*=====================*/
180 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
181 #ifdef CONFIG_XTFPGA_LX60
182 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
183 # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */
184 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
185 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
186 #elif defined(CONFIG_XTFPGA_KC705)
187 # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
188 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
189 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
190 # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000)
192 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
193 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
194 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
195 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
197 #define CONFIG_SYS_MAX_FLASH_SECT \
198 (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
199 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
202 * Put environment in top block (64kB)
203 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB
206 /* print 'E' for empty sector on flinfo */
207 #define CONFIG_SYS_FLASH_EMPTY_INFO
209 #endif /* __CONFIG_H */