1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007-2013 Tensilica, Inc.
4 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
10 #include <asm/arch/core.h>
11 #include <asm/addrspace.h>
12 #include <asm/config.h>
15 * The 'xtfpga' board describes a set of very similar boards with only minimal
19 /*=====================*/
20 /* Board and Processor */
21 /*=====================*/
25 /*===================*/
27 /*===================*/
29 #if XCHAL_HAVE_PTP_MMU
30 #define CONFIG_SYS_MEMORY_BASE \
31 (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
32 #define CONFIG_SYS_IO_BASE 0xf0000000
34 #define CONFIG_SYS_MEMORY_BASE 0x60000000
35 #define CONFIG_SYS_IO_BASE 0x90000000
36 #define CONFIG_MAX_MEM_MAPPED 0x10000000
41 * LX60 0x04000000 64 MB
42 * LX110 0x03000000 48 MB
43 * LX200 0x06000000 96 MB
44 * ML605 0x18000000 384 MB
45 * KC705 0x38000000 896 MB
47 * noMMU configurations can only see first 256MB of onboard memory.
50 #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
51 #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
53 #define CONFIG_SYS_SDRAM_SIZE 0x10000000
56 #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
58 /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
59 #ifdef CONFIG_XTFPGA_LX60
60 # define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */
62 # define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */
65 /* Memory test is destructive so default must not overlap vectors or U-Boot*/
67 /* Load address for stand-alone applications.
68 * MEMADDR cannot be used here, because the definition needs to be
69 * a plain number as it's used as -Ttext argument for ld in standalone
71 * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually.
73 #if XCHAL_HAVE_PTP_MMU
74 #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR
75 #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000
77 #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000
80 #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000
83 #if defined(CONFIG_MAX_MEM_MAPPED) && \
84 CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE
85 #define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED
87 #define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE
90 #define XTENSA_SYS_TEXT_ADDR \
91 (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN)
93 /*==============================*/
94 /* U-Boot general configuration */
95 /*==============================*/
97 /* Console I/O Buffer Size */
98 /*==============================*/
99 /* U-Boot autoboot configuration */
100 /*==============================*/
103 /*=========================================*/
104 /* FPGA Registers (board info and control) */
105 /*=========================================*/
108 * These assume FPGA bitstreams from Tensilica release RB and up. Earlier
109 * releases may not provide any/all of these registers or at these offsets.
110 * Some of the FPGA registers are broken down into bitfields described by
111 * SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
114 /* Date of FPGA bitstream build in binary coded decimal (BCD) */
115 #define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000)
116 #define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */
117 #define FPGAREG_MTH_WIDTH 8
118 #define FPGAREG_MTH_MASK 0xFF000000
119 #define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */
120 #define FPGAREG_DAY_WIDTH 8
121 #define FPGAREG_DAY_MASK 0x00FF0000
122 #define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/
123 #define FPGAREG_YEAR_WIDTH 16
124 #define FPGAREG_YEAR_MASK 0x0000FFFF
126 /* FPGA core clock frequency in Hz (also input to UART) */
127 #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
130 * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
131 * Bits 0..5 set the lower 6 bits of the default ethernet MAC.
132 * Bit 6 is reserved for future use by Tensilica.
133 * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to
134 * the base of flash * (when on/1) or to the base of RAM (when off/0).
136 #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
137 #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
138 #define FPGAREG_MAC_WIDTH 6
139 #define FPGAREG_MAC_MASK 0x3f
140 #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */
141 #define FPGAREG_BOOT_WIDTH 1
142 #define FPGAREG_BOOT_MASK 0x80
143 #define FPGAREG_BOOT_RAM 0
144 #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
146 /* Force hard reset of board by writing a code to this register */
147 #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
148 #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
150 /*====================*/
151 /* Serial Driver Info */
152 /*====================*/
154 #define CONFIG_SYS_NS16550_SERIAL
155 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
156 #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
158 /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
159 #define CONFIG_SYS_NS16550_CLK get_board_sys_clk()
161 /*======================*/
162 /* Ethernet Driver Info */
163 /*======================*/
165 #define CONFIG_ETHBASE 00:50:C2:13:6f:00
166 #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000)
167 #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
169 /*=====================*/
170 /* Flash & Environment */
171 /*=====================*/
173 #ifdef CONFIG_XTFPGA_LX60
174 # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
175 # define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* block size 64KB */
176 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
177 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
178 #elif defined(CONFIG_XTFPGA_KC705)
179 # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
180 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
181 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
182 # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000)
184 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
185 # define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* block size 128KB */
186 # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
187 # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000)
189 #define CONFIG_SYS_MAX_FLASH_SECT \
190 (CONFIG_SYS_FLASH_SECT_SZ/CONFIG_SYS_FLASH_PARMSECT_SZ + \
191 CONFIG_SYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ - 1)
194 * Put environment in top block (64kB)
195 * Another option would be to put env. in 2nd param block offs 8KB, size 8KB
198 /* print 'E' for empty sector on flinfo */
199 #define CONFIG_SYS_FLASH_EMPTY_INFO
201 #endif /* __CONFIG_H */