include/configs/xpedite550x.h

   1 /*
   2  * Copyright 2010 Extreme Engineering Solutions, Inc.
   3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * xpedite550x board configuration file
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_BOOKE            1       /* BOOKE */
  18 #define CONFIG_E500             1       /* BOOKE e500 family */
  19 #define CONFIG_P2020            1
  20 #define CONFIG_XPEDITE550X      1
  21 #define CONFIG_SYS_BOARD_NAME   "XPedite5500"
  22 #define CONFIG_SYS_FORM_PMC_XMC 1
  23 #define CONFIG_PRPMC_PCI_ALIAS  "pci0"  /* Processor PMC interface on pci0 */
  24 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_pre_init */
  25 #define CONFIG_DISPLAY_BOARDINFO
  26
  27 #ifndef CONFIG_SYS_TEXT_BASE
  28 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  29 #endif
  30
  31 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
  32 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play */
  33 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  34 #define CONFIG_PCIE1            1       /* PCIE controler 1 (PEX8112 or XMC) */
  35 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  36 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  37 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  38 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  39 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  40 #define CONFIG_FSL_ELBC         1
  41
  42 /*
  43  * Multicore config
  44  */
  45 #define CONFIG_MP
  46 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  47 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  48
  49 /*
  50  * DDR config
  51  */
  52 #define CONFIG_SYS_FSL_DDR3
  53 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  54 #define CONFIG_DDR_SPD
  55 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  56 #define SPD_EEPROM_ADDRESS                      0x54
  57 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  58 #define CONFIG_NUM_DDR_CONTROLLERS      1
  59 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  60 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  61 #define CONFIG_DDR_ECC
  62 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  63 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  64 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  65 #define CONFIG_VERY_BIG_RAM
  66
  67 #ifndef __ASSEMBLY__
  68 extern unsigned long get_board_sys_clk(unsigned long dummy);
  69 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  70 #endif
  71
  72 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  73 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  74
  75 /*
  76  * These can be toggled for performance analysis, otherwise use default.
  77  */
  78 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  79 #define CONFIG_BTB                      /* toggle branch predition */
  80 #define CONFIG_ENABLE_36BIT_PHYS        1
  81
  82 #define CONFIG_SYS_CCSRBAR              0xef000000
  83 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  84
  85 /*
  86  * Diagnostics
  87  */
  88 #define CONFIG_SYS_ALT_MEMTEST
  89 #define CONFIG_SYS_MEMTEST_START        0x10000000
  90 #define CONFIG_SYS_MEMTEST_END          0x20000000
  91 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
  92                                          CONFIG_SYS_POST_I2C)
  93 #define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_EEPROM_ADDR,    \
  94                                          CONFIG_SYS_I2C_LM75_ADDR,      \
  95                                          CONFIG_SYS_I2C_LM90_ADDR,      \
  96                                          CONFIG_SYS_I2C_PCA953X_ADDR0,  \
  97                                          CONFIG_SYS_I2C_PCA953X_ADDR2,  \
  98                                          CONFIG_SYS_I2C_PCA953X_ADDR3,  \
  99                                          CONFIG_SYS_I2C_RTC_ADDR}
 100
 101 /*
 102  * Memory map
 103  * 0x0000_0000 0x7fff_ffff      DDR                     2G Cacheable
 104  * 0x8000_0000 0xbfff_ffff      PCIe1 Mem               1G non-cacheable
 105  * 0xe000_0000 0xe7ff_ffff      SRAM/SSRAM/L1 Cache     128M non-cacheable
 106  * 0xe800_0000 0xe87f_ffff      PCIe1 IO                8M non-cacheable
 107  * 0xee00_0000 0xee00_ffff      Boot page translation   4K non-cacheable
 108  * 0xef00_0000 0xef0f_ffff      CCSR/IMMR               1M non-cacheable
 109  * 0xef80_0000 0xef8f_ffff      NAND Flash              1M non-cacheable
 110  * 0xf000_0000 0xf7ff_ffff      NOR Flash 2             128M non-cacheable
 111  * 0xf800_0000 0xffff_ffff      NOR Flash 1             128M non-cacheable
 112  */
 113
 114 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
 115
 116 /*
 117  * NAND flash configuration
 118  */
 119 #define CONFIG_SYS_NAND_BASE            0xef800000
 120 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
 121 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
 122                                          CONFIG_SYS_NAND_BASE2}
 123 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 124 #define CONFIG_NAND_FSL_ELBC
 125
 126 /*
 127  * NOR flash configuration
 128  */
 129 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 130 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 131 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 132 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 133 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 134 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 135 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 136 #define CONFIG_FLASH_CFI_DRIVER
 137 #define CONFIG_SYS_FLASH_CFI
 138 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 139 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 140                                                   {0xf7f40000, 0xc0000} }
 141 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 142
 143 /*
 144  * Chip select configuration
 145  */
 146 /* NOR Flash 0 on CS0 */
 147 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 148                                  BR_PS_16               | \
 149                                  BR_V)
 150 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 151                                  OR_GPCM_CSNT           | \
 152                                  OR_GPCM_XACS           | \
 153                                  OR_GPCM_ACS_DIV2       | \
 154                                  OR_GPCM_SCY_8          | \
 155                                  OR_GPCM_TRLX           | \
 156                                  OR_GPCM_EHTR           | \
 157                                  OR_GPCM_EAD)
 158
 159 /* NOR Flash 1 on CS1 */
 160 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 161                                  BR_PS_16               | \
 162                                  BR_V)
 163 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 164
 165 /* NAND flash on CS2 */
 166 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 167                                  (2<<BR_DECC_SHIFT)     | \
 168                                  BR_PS_8                | \
 169                                  BR_MS_FCM              | \
 170                                  BR_V)
 171
 172 /* NAND flash on CS2 */
 173 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 174                                  OR_FCM_PGS     | \
 175                                  OR_FCM_CSCT    | \
 176                                  OR_FCM_CST     | \
 177                                  OR_FCM_CHT     | \
 178                                  OR_FCM_SCY_1   | \
 179                                  OR_FCM_TRLX    | \
 180                                  OR_FCM_EHTR)
 181
 182 /* NAND flash on CS3 */
 183 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 184                                  (2<<BR_DECC_SHIFT)     | \
 185                                  BR_PS_8                | \
 186                                  BR_MS_FCM              | \
 187                                  BR_V)
 188 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 189
 190 /*
 191  * Use L1 as initial stack
 192  */
 193 #define CONFIG_SYS_INIT_RAM_LOCK        1
 194 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 195 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 196
 197 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 198 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 199
 200 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 201 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 202
 203 /*
 204  * Serial Port
 205  */
 206 #define CONFIG_CONS_INDEX               1
 207 #define CONFIG_SYS_NS16550_SERIAL
 208 #define CONFIG_SYS_NS16550_REG_SIZE     1
 209 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 210 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 211 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 212 #define CONFIG_SYS_BAUDRATE_TABLE       \
 213         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 214 #define CONFIG_BAUDRATE                 115200
 215 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 216 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 217
 218 /*
 219  * Use the HUSH parser
 220  */
 221 #define CONFIG_SYS_HUSH_PARSER
 222
 223 /*
 224  * Pass open firmware flat tree
 225  */
 226 #define CONFIG_OF_LIBFDT                1
 227 #define CONFIG_OF_BOARD_SETUP           1
 228 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 229 #define CONFIG_FDT_FIXUP_PCI_IRQ        1
 230
 231 /*
 232  * I2C
 233  */
 234 #define CONFIG_SYS_I2C
 235 #define CONFIG_SYS_I2C_FSL
 236 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 237 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 238 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 239 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 240 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 241 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 242
 243 /* I2C DS7505 temperature sensor */
 244 #define CONFIG_DTT_LM75
 245 #define CONFIG_DTT_SENSORS              { 0 }
 246 #define CONFIG_SYS_I2C_LM75_ADDR        0x48
 247
 248 /* I2C ADT7461 temperature sensor */
 249 #define CONFIG_SYS_I2C_LM90_ADDR        0x4C
 250
 251 /* I2C EEPROM - AT24C128B */
 252 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 253 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 254 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 255 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 256
 257 /* I2C RTC */
 258 #define CONFIG_RTC_M41T11               1
 259 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 260 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 261
 262 /* GPIO */
 263 #define CONFIG_PCA953X
 264 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 265 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 266 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 267 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 268 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 269
 270 /*
 271  * GPIO pin definitions, PU = pulled high, PD = pulled low
 272  */
 273 /* PCA9557 @ 0x18*/
 274 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 275 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
 276 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 277 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
 278 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 279 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Write protection (0: disabled, 1: enabled) */
 280
 281 /* PCA9557 @ 0x1e*/
 282 #define CONFIG_SYS_PCA953X_XMC_GA0              0x01 /* PU; */
 283 #define CONFIG_SYS_PCA953X_XMC_GA1              0x02 /* PU; */
 284 #define CONFIG_SYS_PCA953X_XMC_GA2              0x04 /* PU; */
 285 #define CONFIG_SYS_PCA953X_XMC_WAKE             0x10 /* PU; */
 286 #define CONFIG_SYS_PCA953X_XMC_BIST             0x20 /* Enable XMC BIST */
 287 #define CONFIG_SYS_PCA953X_PMC_EREADY           0x40 /* PU; PMC PCI eready */
 288 #define CONFIG_SYS_PCA953X_PMC_MONARCH          0x80 /* PMC monarch mode enable */
 289
 290 /* PCA9557 @ 0x1f */
 291 #define CONFIG_SYS_PCA953X_MC_GPIO0             0x01 /* PU; */
 292 #define CONFIG_SYS_PCA953X_MC_GPIO1             0x02 /* PU; */
 293 #define CONFIG_SYS_PCA953X_MC_GPIO2             0x04 /* PU; */
 294 #define CONFIG_SYS_PCA953X_MC_GPIO3             0x08 /* PU; */
 295 #define CONFIG_SYS_PCA953X_MC_GPIO4             0x10 /* PU; */
 296 #define CONFIG_SYS_PCA953X_MC_GPIO5             0x20 /* PU; */
 297 #define CONFIG_SYS_PCA953X_MC_GPIO6             0x40 /* PU; */
 298 #define CONFIG_SYS_PCA953X_MC_GPIO7             0x80 /* PU; */
 299
 300 /*
 301  * General PCI
 302  * Memory space is mapped 1-1, but I/O space must start from 0.
 303  */
 304
 305 /* controller 1 - PEX8112 or XMC, depending on build option */
 306 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 307 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 308 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 309 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 310 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 311 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 312
 313
 314 /*
 315  * Networking options
 316  */
 317 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 318 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 319 #define CONFIG_TSEC_TBI
 320 #define CONFIG_MII              1       /* MII PHY management */
 321 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 322 #define CONFIG_ETHPRIME         "eTSEC2"
 323
 324 /*
 325  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 326  * 1000mbps SGMII link
 327  */
 328 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 329                 TBICR_PHY_RESET \
 330                 | TBICR_FULL_DUPLEX \
 331                 | TBICR_SPEED1_SET \
 332                 )
 333
 334 #define CONFIG_TSEC1            1
 335 #define CONFIG_TSEC1_NAME       "eTSEC1"
 336 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 337 #define TSEC1_PHY_ADDR          1
 338 #define TSEC1_PHYIDX            0
 339 #define CONFIG_HAS_ETH0
 340
 341 #define CONFIG_TSEC2            1
 342 #define CONFIG_TSEC2_NAME       "eTSEC2"
 343 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 344 #define TSEC2_PHY_ADDR          2
 345 #define TSEC2_PHYIDX            0
 346 #define CONFIG_HAS_ETH1
 347
 348 #define CONFIG_TSEC3            1
 349 #define CONFIG_TSEC3_NAME       "eTSEC3"
 350 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 351 #define TSEC3_PHY_ADDR          3
 352 #define TSEC3_PHYIDX            0
 353 #define CONFIG_HAS_ETH2
 354
 355 /*
 356  * USB
 357  */
 358 #define CONFIG_USB_STORAGE
 359 #define CONFIG_USB_EHCI
 360 #define CONFIG_USB_EHCI_FSL
 361 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 362 #define CONFIG_DOS_PARTITION
 363
 364 /*
 365  * Command configuration.
 366  */
 367 #define CONFIG_CMD_ASKENV
 368 #define CONFIG_CMD_DATE
 369 #define CONFIG_CMD_DHCP
 370 #define CONFIG_CMD_DTT
 371 #define CONFIG_CMD_EEPROM
 372 #define CONFIG_CMD_I2C
 373 #define CONFIG_CMD_JFFS2
 374 #define CONFIG_CMD_MII
 375 #define CONFIG_CMD_NAND
 376 #define CONFIG_CMD_PCA953X
 377 #define CONFIG_CMD_PCA953X_INFO
 378 #define CONFIG_CMD_PCI
 379 #define CONFIG_CMD_PCI_ENUM
 380 #define CONFIG_CMD_PING
 381 #define CONFIG_CMD_REGINFO
 382 #define CONFIG_CMD_SNTP
 383 #define CONFIG_CMD_USB
 384
 385 /*
 386  * Miscellaneous configurable options
 387  */
 388 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 389 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 390 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 391 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 392 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 393 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 394 #define CONFIG_CMDLINE_EDITING  1               /* add command line history     */
 395 #define CONFIG_AUTO_COMPLETE    1               /* add autocompletion support */
 396 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 397 #define CONFIG_BOOTDELAY        3               /* -1 disables auto-boot */
 398 #define CONFIG_PANIC_HANG                       /* do not reset board on panic */
 399 #define CONFIG_PREBOOT                          /* enable preboot variable */
 400 #define CONFIG_FIT              1
 401 #define CONFIG_FIT_VERBOSE      1
 402 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 403
 404 /*
 405  * For booting Linux, the board info and command line data
 406  * have to be in the first 16 MB of memory, since this is
 407  * the maximum mapped by the Linux kernel during initialization.
 408  */
 409 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 410 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 411
 412 /*
 413  * Environment Configuration
 414  */
 415 #define CONFIG_ENV_IS_IN_FLASH  1
 416 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 417 #define CONFIG_ENV_SIZE         0x8000
 418 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
 419
 420 /*
 421  * Flash memory map:
 422  * fff80000 - ffffffff     Pri U-Boot (512 KB)
 423  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 424  * fff00000 - fff3ffff     Pri FDT (256KB)
 425  * fef00000 - ffefffff     Pri OS image (16MB)
 426  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 427  *
 428  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 429  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 430  * f7f00000 - f7f3ffff     Sec FDT (256KB)
 431  * f6f00000 - f7efffff     Sec OS image (16MB)
 432  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 433  */
 434 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
 435 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
 436 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
 437 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
 438 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 439 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 440
 441 #define CONFIG_PROG_UBOOT1                                              \
 442         "$download_cmd $loadaddr $ubootfile; "                          \
 443         "if test $? -eq 0; then "                                       \
 444                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 445                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 446                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 447                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 448                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 449                 "if test $? -ne 0; then "                               \
 450                         "echo PROGRAM FAILED; "                         \
 451                 "else; "                                                \
 452                         "echo PROGRAM SUCCEEDED; "                      \
 453                 "fi; "                                                  \
 454         "else; "                                                        \
 455                 "echo DOWNLOAD FAILED; "                                \
 456         "fi;"
 457
 458 #define CONFIG_PROG_UBOOT2                                              \
 459         "$download_cmd $loadaddr $ubootfile; "                          \
 460         "if test $? -eq 0; then "                                       \
 461                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 462                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 463                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 464                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 465                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 466                 "if test $? -ne 0; then "                               \
 467                         "echo PROGRAM FAILED; "                         \
 468                 "else; "                                                \
 469                         "echo PROGRAM SUCCEEDED; "                      \
 470                 "fi; "                                                  \
 471         "else; "                                                        \
 472                 "echo DOWNLOAD FAILED; "                                \
 473         "fi;"
 474
 475 #define CONFIG_BOOT_OS_NET                                              \
 476         "$download_cmd $osaddr $osfile; "                               \
 477         "if test $? -eq 0; then "                                       \
 478                 "if test -n $fdtaddr; then "                            \
 479                         "$download_cmd $fdtaddr $fdtfile; "             \
 480                         "if test $? -eq 0; then "                       \
 481                                 "bootm $osaddr - $fdtaddr; "            \
 482                         "else; "                                        \
 483                                 "echo FDT DOWNLOAD FAILED; "            \
 484                         "fi; "                                          \
 485                 "else; "                                                \
 486                         "bootm $osaddr; "                               \
 487                 "fi; "                                                  \
 488         "else; "                                                        \
 489                 "echo OS DOWNLOAD FAILED; "                             \
 490         "fi;"
 491
 492 #define CONFIG_PROG_OS1                                                 \
 493         "$download_cmd $osaddr $osfile; "                               \
 494         "if test $? -eq 0; then "                                       \
 495                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 496                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 497                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 498                 "if test $? -ne 0; then "                               \
 499                         "echo OS PROGRAM FAILED; "                      \
 500                 "else; "                                                \
 501                         "echo OS PROGRAM SUCCEEDED; "                   \
 502                 "fi; "                                                  \
 503         "else; "                                                        \
 504                 "echo OS DOWNLOAD FAILED; "                             \
 505         "fi;"
 506
 507 #define CONFIG_PROG_OS2                                                 \
 508         "$download_cmd $osaddr $osfile; "                               \
 509         "if test $? -eq 0; then "                                       \
 510                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 511                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 512                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 513                 "if test $? -ne 0; then "                               \
 514                         "echo OS PROGRAM FAILED; "                      \
 515                 "else; "                                                \
 516                         "echo OS PROGRAM SUCCEEDED; "                   \
 517                 "fi; "                                                  \
 518         "else; "                                                        \
 519                 "echo OS DOWNLOAD FAILED; "                             \
 520         "fi;"
 521
 522 #define CONFIG_PROG_FDT1                                                \
 523         "$download_cmd $fdtaddr $fdtfile; "                             \
 524         "if test $? -eq 0; then "                                       \
 525                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 526                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 527                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 528                 "if test $? -ne 0; then "                               \
 529                         "echo FDT PROGRAM FAILED; "                     \
 530                 "else; "                                                \
 531                         "echo FDT PROGRAM SUCCEEDED; "                  \
 532                 "fi; "                                                  \
 533         "else; "                                                        \
 534                 "echo FDT DOWNLOAD FAILED; "                            \
 535         "fi;"
 536
 537 #define CONFIG_PROG_FDT2                                                \
 538         "$download_cmd $fdtaddr $fdtfile; "                             \
 539         "if test $? -eq 0; then "                                       \
 540                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 541                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 542                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 543                 "if test $? -ne 0; then "                               \
 544                         "echo FDT PROGRAM FAILED; "                     \
 545                 "else; "                                                \
 546                         "echo FDT PROGRAM SUCCEEDED; "                  \
 547                 "fi; "                                                  \
 548         "else; "                                                        \
 549                 "echo FDT DOWNLOAD FAILED; "                            \
 550         "fi;"
 551
 552 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 553         "autoload=yes\0"                                                \
 554         "download_cmd=tftp\0"                                           \
 555         "console_args=console=ttyS0,115200\0"                           \
 556         "root_args=root=/dev/nfs rw\0"                                  \
 557         "misc_args=ip=on\0"                                             \
 558         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 559         "bootfile=/home/user/file\0"                                    \
 560         "osfile=/home/user/board.uImage\0"                              \
 561         "fdtfile=/home/user/board.dtb\0"                                \
 562         "ubootfile=/home/user/u-boot.bin\0"                             \
 563         "fdtaddr=c00000\0"                                              \
 564         "osaddr=0x1000000\0"                                            \
 565         "loadaddr=0x1000000\0"                                          \
 566         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 567         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 568         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 569         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 570         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 571         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 572         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 573         "bootcmd_flash1=run set_bootargs; "                             \
 574                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 575         "bootcmd_flash2=run set_bootargs; "                             \
 576                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 577         "bootcmd=run bootcmd_flash1\0"
 578 #endif  /* __CONFIG_H */