1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010 Extreme Engineering Solutions, Inc.
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
8 * xpedite550x board configuration file
14 * High Level Configuration Options
16 #define CONFIG_SYS_BOARD_NAME "XPedite5500"
17 #define CONFIG_SYS_FORM_PMC_XMC 1
18 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
20 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
21 #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
22 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
23 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
29 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
30 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
35 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
36 #define CONFIG_DDR_SPD
37 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
38 #define SPD_EEPROM_ADDRESS 0x54
39 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
40 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
41 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
42 #define CONFIG_DDR_ECC
43 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
46 #define CONFIG_VERY_BIG_RAM
49 extern unsigned long get_board_sys_clk(unsigned long dummy);
50 extern unsigned long get_board_ddr_clk(unsigned long dummy);
53 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
54 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
57 * These can be toggled for performance analysis, otherwise use default.
59 #define CONFIG_L2_CACHE /* toggle L2 cache */
60 #define CONFIG_BTB /* toggle branch predition */
61 #define CONFIG_ENABLE_36BIT_PHYS 1
63 #define CONFIG_SYS_CCSRBAR 0xef000000
64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
69 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
71 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
72 CONFIG_SYS_I2C_LM75_ADDR, \
73 CONFIG_SYS_I2C_LM90_ADDR, \
74 CONFIG_SYS_I2C_PCA953X_ADDR0, \
75 CONFIG_SYS_I2C_PCA953X_ADDR2, \
76 CONFIG_SYS_I2C_PCA953X_ADDR3, \
77 CONFIG_SYS_I2C_RTC_ADDR}
81 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
82 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
83 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
84 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
85 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
86 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
87 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
88 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
89 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
92 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
95 * NAND flash configuration
97 #define CONFIG_SYS_NAND_BASE 0xef800000
98 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
99 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
100 CONFIG_SYS_NAND_BASE2}
101 #define CONFIG_SYS_MAX_NAND_DEVICE 2
102 #define CONFIG_NAND_FSL_ELBC
105 * NOR flash configuration
107 #define CONFIG_SYS_FLASH_BASE 0xf8000000
108 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
109 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
110 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
111 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
112 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
113 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
114 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
115 {0xf7f40000, 0xc0000} }
116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
119 * Chip select configuration
121 /* NOR Flash 0 on CS0 */
122 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
125 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
134 /* NOR Flash 1 on CS1 */
135 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
138 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
140 /* NAND flash on CS2 */
141 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
142 (2<<BR_DECC_SHIFT) | \
147 /* NAND flash on CS2 */
148 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
157 /* NAND flash on CS3 */
158 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
159 (2<<BR_DECC_SHIFT) | \
163 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
166 * Use L1 as initial stack
168 #define CONFIG_SYS_INIT_RAM_LOCK 1
169 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
170 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
172 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
173 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
175 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
176 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
181 #define CONFIG_SYS_NS16550_SERIAL
182 #define CONFIG_SYS_NS16550_REG_SIZE 1
183 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
184 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
185 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
186 #define CONFIG_SYS_BAUDRATE_TABLE \
187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
188 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
189 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
195 #define CONFIG_SYS_I2C
196 #define CONFIG_SYS_I2C_FSL
197 #define CONFIG_SYS_FSL_I2C_SPEED 400000
198 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
199 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
200 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
201 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
202 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
204 /* I2C DS7505 temperature sensor */
205 #define CONFIG_SYS_I2C_LM75_ADDR 0x48
207 /* I2C ADT7461 temperature sensor */
208 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C
210 /* I2C EEPROM - AT24C128B */
211 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
212 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
213 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
217 #define CONFIG_RTC_M41T11 1
218 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
219 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
222 #define CONFIG_PCA953X
223 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
224 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
225 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
226 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
227 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
230 * GPIO pin definitions, PU = pulled high, PD = pulled low
233 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
234 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
235 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
236 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
237 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
238 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
241 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
242 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
243 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
244 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
245 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
246 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
247 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
250 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
251 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
252 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
253 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
254 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
255 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
256 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
257 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
261 * Memory space is mapped 1-1, but I/O space must start from 0.
264 /* controller 1 - PEX8112 or XMC, depending on build option */
265 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
266 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
267 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
268 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
269 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
270 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
275 #define CONFIG_TSEC_TBI
276 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
277 #define CONFIG_ETHPRIME "eTSEC2"
280 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
281 * 1000mbps SGMII link
283 #define CONFIG_TSEC_TBICR_SETTINGS ( \
285 | TBICR_FULL_DUPLEX \
289 #define CONFIG_TSEC1 1
290 #define CONFIG_TSEC1_NAME "eTSEC1"
291 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
292 #define TSEC1_PHY_ADDR 1
293 #define TSEC1_PHYIDX 0
294 #define CONFIG_HAS_ETH0
296 #define CONFIG_TSEC2 1
297 #define CONFIG_TSEC2_NAME "eTSEC2"
298 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
299 #define TSEC2_PHY_ADDR 2
300 #define TSEC2_PHYIDX 0
301 #define CONFIG_HAS_ETH1
303 #define CONFIG_TSEC3 1
304 #define CONFIG_TSEC3_NAME "eTSEC3"
305 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
306 #define TSEC3_PHY_ADDR 3
307 #define TSEC3_PHYIDX 0
308 #define CONFIG_HAS_ETH2
313 #define CONFIG_USB_EHCI_FSL
314 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
317 * Miscellaneous configurable options
319 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
320 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
321 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
324 * For booting Linux, the board info and command line data
325 * have to be in the first 16 MB of memory, since this is
326 * the maximum mapped by the Linux kernel during initialization.
328 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
329 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
332 * Environment Configuration
337 * fff80000 - ffffffff Pri U-Boot (512 KB)
338 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
339 * fff00000 - fff3ffff Pri FDT (256KB)
340 * fef00000 - ffefffff Pri OS image (16MB)
341 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
343 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
344 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
345 * f7f00000 - f7f3ffff Sec FDT (256KB)
346 * f6f00000 - f7efffff Sec OS image (16MB)
347 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
349 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
350 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
351 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
352 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
353 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
354 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
356 #define CONFIG_PROG_UBOOT1 \
357 "$download_cmd $loadaddr $ubootfile; " \
358 "if test $? -eq 0; then " \
359 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
360 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
361 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
362 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
363 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
364 "if test $? -ne 0; then " \
365 "echo PROGRAM FAILED; " \
367 "echo PROGRAM SUCCEEDED; " \
370 "echo DOWNLOAD FAILED; " \
373 #define CONFIG_PROG_UBOOT2 \
374 "$download_cmd $loadaddr $ubootfile; " \
375 "if test $? -eq 0; then " \
376 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
377 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
378 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
379 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
380 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
381 "if test $? -ne 0; then " \
382 "echo PROGRAM FAILED; " \
384 "echo PROGRAM SUCCEEDED; " \
387 "echo DOWNLOAD FAILED; " \
390 #define CONFIG_BOOT_OS_NET \
391 "$download_cmd $osaddr $osfile; " \
392 "if test $? -eq 0; then " \
393 "if test -n $fdtaddr; then " \
394 "$download_cmd $fdtaddr $fdtfile; " \
395 "if test $? -eq 0; then " \
396 "bootm $osaddr - $fdtaddr; " \
398 "echo FDT DOWNLOAD FAILED; " \
404 "echo OS DOWNLOAD FAILED; " \
407 #define CONFIG_PROG_OS1 \
408 "$download_cmd $osaddr $osfile; " \
409 "if test $? -eq 0; then " \
410 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
411 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
412 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
413 "if test $? -ne 0; then " \
414 "echo OS PROGRAM FAILED; " \
416 "echo OS PROGRAM SUCCEEDED; " \
419 "echo OS DOWNLOAD FAILED; " \
422 #define CONFIG_PROG_OS2 \
423 "$download_cmd $osaddr $osfile; " \
424 "if test $? -eq 0; then " \
425 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
426 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
427 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
428 "if test $? -ne 0; then " \
429 "echo OS PROGRAM FAILED; " \
431 "echo OS PROGRAM SUCCEEDED; " \
434 "echo OS DOWNLOAD FAILED; " \
437 #define CONFIG_PROG_FDT1 \
438 "$download_cmd $fdtaddr $fdtfile; " \
439 "if test $? -eq 0; then " \
440 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
441 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
442 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
443 "if test $? -ne 0; then " \
444 "echo FDT PROGRAM FAILED; " \
446 "echo FDT PROGRAM SUCCEEDED; " \
449 "echo FDT DOWNLOAD FAILED; " \
452 #define CONFIG_PROG_FDT2 \
453 "$download_cmd $fdtaddr $fdtfile; " \
454 "if test $? -eq 0; then " \
455 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
456 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
457 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
458 "if test $? -ne 0; then " \
459 "echo FDT PROGRAM FAILED; " \
461 "echo FDT PROGRAM SUCCEEDED; " \
464 "echo FDT DOWNLOAD FAILED; " \
467 #define CONFIG_EXTRA_ENV_SETTINGS \
469 "download_cmd=tftp\0" \
470 "console_args=console=ttyS0,115200\0" \
471 "root_args=root=/dev/nfs rw\0" \
472 "misc_args=ip=on\0" \
473 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
474 "bootfile=/home/user/file\0" \
475 "osfile=/home/user/board.uImage\0" \
476 "fdtfile=/home/user/board.dtb\0" \
477 "ubootfile=/home/user/u-boot.bin\0" \
478 "fdtaddr=0x1e00000\0" \
479 "osaddr=0x1000000\0" \
480 "loadaddr=0x1000000\0" \
481 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
482 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
483 "prog_os1="CONFIG_PROG_OS1"\0" \
484 "prog_os2="CONFIG_PROG_OS2"\0" \
485 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
486 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
487 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
488 "bootcmd_flash1=run set_bootargs; " \
489 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
490 "bootcmd_flash2=run set_bootargs; " \
491 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
492 "bootcmd=run bootcmd_flash1\0"
493 #endif /* __CONFIG_H */