include/configs/xpedite550x.h

   1 /*
   2  * Copyright 2010 Extreme Engineering Solutions, Inc.
   3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * xpedite550x board configuration file
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_BOOKE            1       /* BOOKE */
  18 #define CONFIG_E500             1       /* BOOKE e500 family */
  19 #define CONFIG_P2020            1
  20 #define CONFIG_XPEDITE550X      1
  21 #define CONFIG_SYS_BOARD_NAME   "XPedite5500"
  22 #define CONFIG_SYS_FORM_PMC_XMC 1
  23 #define CONFIG_PRPMC_PCI_ALIAS  "pci0"  /* Processor PMC interface on pci0 */
  24 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_pre_init */
  25
  26 #ifndef CONFIG_SYS_TEXT_BASE
  27 #define CONFIG_SYS_TEXT_BASE    0xfff80000
  28 #endif
  29
  30 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  31 #define CONFIG_PCIE1            1       /* PCIE controller 1 (PEX8112 or XMC) */
  32 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  33 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  34 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  35 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  36 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  37 #define CONFIG_FSL_ELBC         1
  38
  39 /*
  40  * Multicore config
  41  */
  42 #define CONFIG_MP
  43 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  44 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  45
  46 /*
  47  * DDR config
  48  */
  49 #define CONFIG_SYS_FSL_DDR3
  50 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  51 #define CONFIG_DDR_SPD
  52 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  53 #define SPD_EEPROM_ADDRESS                      0x54
  54 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  55 #define CONFIG_NUM_DDR_CONTROLLERS      1
  56 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  57 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  58 #define CONFIG_DDR_ECC
  59 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  60 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  61 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  62 #define CONFIG_VERY_BIG_RAM
  63
  64 #ifndef __ASSEMBLY__
  65 extern unsigned long get_board_sys_clk(unsigned long dummy);
  66 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  67 #endif
  68
  69 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  70 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  71
  72 /*
  73  * These can be toggled for performance analysis, otherwise use default.
  74  */
  75 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  76 #define CONFIG_BTB                      /* toggle branch predition */
  77 #define CONFIG_ENABLE_36BIT_PHYS        1
  78
  79 #define CONFIG_SYS_CCSRBAR              0xef000000
  80 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  81
  82 /*
  83  * Diagnostics
  84  */
  85 #define CONFIG_SYS_ALT_MEMTEST
  86 #define CONFIG_SYS_MEMTEST_START        0x10000000
  87 #define CONFIG_SYS_MEMTEST_END          0x20000000
  88 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
  89                                          CONFIG_SYS_POST_I2C)
  90 #define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_EEPROM_ADDR,    \
  91                                          CONFIG_SYS_I2C_LM75_ADDR,      \
  92                                          CONFIG_SYS_I2C_LM90_ADDR,      \
  93                                          CONFIG_SYS_I2C_PCA953X_ADDR0,  \
  94                                          CONFIG_SYS_I2C_PCA953X_ADDR2,  \
  95                                          CONFIG_SYS_I2C_PCA953X_ADDR3,  \
  96                                          CONFIG_SYS_I2C_RTC_ADDR}
  97
  98 /*
  99  * Memory map
 100  * 0x0000_0000 0x7fff_ffff      DDR                     2G Cacheable
 101  * 0x8000_0000 0xbfff_ffff      PCIe1 Mem               1G non-cacheable
 102  * 0xe000_0000 0xe7ff_ffff      SRAM/SSRAM/L1 Cache     128M non-cacheable
 103  * 0xe800_0000 0xe87f_ffff      PCIe1 IO                8M non-cacheable
 104  * 0xee00_0000 0xee00_ffff      Boot page translation   4K non-cacheable
 105  * 0xef00_0000 0xef0f_ffff      CCSR/IMMR               1M non-cacheable
 106  * 0xef80_0000 0xef8f_ffff      NAND Flash              1M non-cacheable
 107  * 0xf000_0000 0xf7ff_ffff      NOR Flash 2             128M non-cacheable
 108  * 0xf800_0000 0xffff_ffff      NOR Flash 1             128M non-cacheable
 109  */
 110
 111 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
 112
 113 /*
 114  * NAND flash configuration
 115  */
 116 #define CONFIG_SYS_NAND_BASE            0xef800000
 117 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
 118 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
 119                                          CONFIG_SYS_NAND_BASE2}
 120 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 121 #define CONFIG_NAND_FSL_ELBC
 122
 123 /*
 124  * NOR flash configuration
 125  */
 126 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 127 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 128 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 129 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 130 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 131 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 132 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 133 #define CONFIG_FLASH_CFI_DRIVER
 134 #define CONFIG_SYS_FLASH_CFI
 135 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 136 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 137                                                   {0xf7f40000, 0xc0000} }
 138 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 139
 140 /*
 141  * Chip select configuration
 142  */
 143 /* NOR Flash 0 on CS0 */
 144 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 145                                  BR_PS_16               | \
 146                                  BR_V)
 147 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 148                                  OR_GPCM_CSNT           | \
 149                                  OR_GPCM_XACS           | \
 150                                  OR_GPCM_ACS_DIV2       | \
 151                                  OR_GPCM_SCY_8          | \
 152                                  OR_GPCM_TRLX           | \
 153                                  OR_GPCM_EHTR           | \
 154                                  OR_GPCM_EAD)
 155
 156 /* NOR Flash 1 on CS1 */
 157 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 158                                  BR_PS_16               | \
 159                                  BR_V)
 160 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 161
 162 /* NAND flash on CS2 */
 163 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 164                                  (2<<BR_DECC_SHIFT)     | \
 165                                  BR_PS_8                | \
 166                                  BR_MS_FCM              | \
 167                                  BR_V)
 168
 169 /* NAND flash on CS2 */
 170 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 171                                  OR_FCM_PGS     | \
 172                                  OR_FCM_CSCT    | \
 173                                  OR_FCM_CST     | \
 174                                  OR_FCM_CHT     | \
 175                                  OR_FCM_SCY_1   | \
 176                                  OR_FCM_TRLX    | \
 177                                  OR_FCM_EHTR)
 178
 179 /* NAND flash on CS3 */
 180 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 181                                  (2<<BR_DECC_SHIFT)     | \
 182                                  BR_PS_8                | \
 183                                  BR_MS_FCM              | \
 184                                  BR_V)
 185 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 186
 187 /*
 188  * Use L1 as initial stack
 189  */
 190 #define CONFIG_SYS_INIT_RAM_LOCK        1
 191 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 192 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 193
 194 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 195 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 196
 197 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 198 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 199
 200 /*
 201  * Serial Port
 202  */
 203 #define CONFIG_CONS_INDEX               1
 204 #define CONFIG_SYS_NS16550_SERIAL
 205 #define CONFIG_SYS_NS16550_REG_SIZE     1
 206 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 207 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 208 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 209 #define CONFIG_SYS_BAUDRATE_TABLE       \
 210         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 211 #define CONFIG_BAUDRATE                 115200
 212 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 213 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 214
 215 #define CONFIG_FDT_FIXUP_PCI_IRQ        1
 216
 217 /*
 218  * I2C
 219  */
 220 #define CONFIG_SYS_I2C
 221 #define CONFIG_SYS_I2C_FSL
 222 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 223 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 224 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 225 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 226 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 227 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 228
 229 /* I2C DS7505 temperature sensor */
 230 #define CONFIG_DTT_LM75
 231 #define CONFIG_DTT_SENSORS              { 0 }
 232 #define CONFIG_SYS_I2C_LM75_ADDR        0x48
 233
 234 /* I2C ADT7461 temperature sensor */
 235 #define CONFIG_SYS_I2C_LM90_ADDR        0x4C
 236
 237 /* I2C EEPROM - AT24C128B */
 238 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 239 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 240 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 241 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 242
 243 /* I2C RTC */
 244 #define CONFIG_RTC_M41T11               1
 245 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 246 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 247
 248 /* GPIO */
 249 #define CONFIG_PCA953X
 250 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 251 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 252 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 253 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 254 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 255
 256 /*
 257  * GPIO pin definitions, PU = pulled high, PD = pulled low
 258  */
 259 /* PCA9557 @ 0x18*/
 260 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 261 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
 262 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 263 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
 264 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 265 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Write protection (0: disabled, 1: enabled) */
 266
 267 /* PCA9557 @ 0x1e*/
 268 #define CONFIG_SYS_PCA953X_XMC_GA0              0x01 /* PU; */
 269 #define CONFIG_SYS_PCA953X_XMC_GA1              0x02 /* PU; */
 270 #define CONFIG_SYS_PCA953X_XMC_GA2              0x04 /* PU; */
 271 #define CONFIG_SYS_PCA953X_XMC_WAKE             0x10 /* PU; */
 272 #define CONFIG_SYS_PCA953X_XMC_BIST             0x20 /* Enable XMC BIST */
 273 #define CONFIG_SYS_PCA953X_PMC_EREADY           0x40 /* PU; PMC PCI eready */
 274 #define CONFIG_SYS_PCA953X_PMC_MONARCH          0x80 /* PMC monarch mode enable */
 275
 276 /* PCA9557 @ 0x1f */
 277 #define CONFIG_SYS_PCA953X_MC_GPIO0             0x01 /* PU; */
 278 #define CONFIG_SYS_PCA953X_MC_GPIO1             0x02 /* PU; */
 279 #define CONFIG_SYS_PCA953X_MC_GPIO2             0x04 /* PU; */
 280 #define CONFIG_SYS_PCA953X_MC_GPIO3             0x08 /* PU; */
 281 #define CONFIG_SYS_PCA953X_MC_GPIO4             0x10 /* PU; */
 282 #define CONFIG_SYS_PCA953X_MC_GPIO5             0x20 /* PU; */
 283 #define CONFIG_SYS_PCA953X_MC_GPIO6             0x40 /* PU; */
 284 #define CONFIG_SYS_PCA953X_MC_GPIO7             0x80 /* PU; */
 285
 286 /*
 287  * General PCI
 288  * Memory space is mapped 1-1, but I/O space must start from 0.
 289  */
 290
 291 /* controller 1 - PEX8112 or XMC, depending on build option */
 292 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 293 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 294 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 295 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 296 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 297 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 298
 299 /*
 300  * Networking options
 301  */
 302 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 303 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 304 #define CONFIG_TSEC_TBI
 305 #define CONFIG_MII              1       /* MII PHY management */
 306 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 307 #define CONFIG_ETHPRIME         "eTSEC2"
 308
 309 /*
 310  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 311  * 1000mbps SGMII link
 312  */
 313 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 314                 TBICR_PHY_RESET \
 315                 | TBICR_FULL_DUPLEX \
 316                 | TBICR_SPEED1_SET \
 317                 )
 318
 319 #define CONFIG_TSEC1            1
 320 #define CONFIG_TSEC1_NAME       "eTSEC1"
 321 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 322 #define TSEC1_PHY_ADDR          1
 323 #define TSEC1_PHYIDX            0
 324 #define CONFIG_HAS_ETH0
 325
 326 #define CONFIG_TSEC2            1
 327 #define CONFIG_TSEC2_NAME       "eTSEC2"
 328 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 329 #define TSEC2_PHY_ADDR          2
 330 #define TSEC2_PHYIDX            0
 331 #define CONFIG_HAS_ETH1
 332
 333 #define CONFIG_TSEC3            1
 334 #define CONFIG_TSEC3_NAME       "eTSEC3"
 335 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 336 #define TSEC3_PHY_ADDR          3
 337 #define TSEC3_PHYIDX            0
 338 #define CONFIG_HAS_ETH2
 339
 340 /*
 341  * USB
 342  */
 343 #define CONFIG_USB_EHCI
 344 #define CONFIG_USB_EHCI_FSL
 345 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 346 #define CONFIG_DOS_PARTITION
 347
 348 /*
 349  * Command configuration.
 350  */
 351 #define CONFIG_CMD_DATE
 352 #define CONFIG_CMD_DTT
 353 #define CONFIG_CMD_EEPROM
 354 #define CONFIG_CMD_JFFS2
 355 #define CONFIG_CMD_NAND
 356 #define CONFIG_CMD_PCA953X
 357 #define CONFIG_CMD_PCA953X_INFO
 358 #define CONFIG_CMD_PCI
 359 #define CONFIG_CMD_PCI_ENUM
 360 #define CONFIG_CMD_REGINFO
 361
 362 /*
 363  * Miscellaneous configurable options
 364  */
 365 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 366 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 367 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 368 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 369 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 370 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 371 #define CONFIG_CMDLINE_EDITING  1               /* add command line history     */
 372 #define CONFIG_AUTO_COMPLETE    1               /* add autocompletion support */
 373 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 374 #define CONFIG_PANIC_HANG                       /* do not reset board on panic */
 375 #define CONFIG_PREBOOT                          /* enable preboot variable */
 376 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 377
 378 /*
 379  * For booting Linux, the board info and command line data
 380  * have to be in the first 16 MB of memory, since this is
 381  * the maximum mapped by the Linux kernel during initialization.
 382  */
 383 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 384 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 385
 386 /*
 387  * Environment Configuration
 388  */
 389 #define CONFIG_ENV_IS_IN_FLASH  1
 390 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 391 #define CONFIG_ENV_SIZE         0x8000
 392 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
 393
 394 /*
 395  * Flash memory map:
 396  * fff80000 - ffffffff     Pri U-Boot (512 KB)
 397  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 398  * fff00000 - fff3ffff     Pri FDT (256KB)
 399  * fef00000 - ffefffff     Pri OS image (16MB)
 400  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 401  *
 402  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 403  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 404  * f7f00000 - f7f3ffff     Sec FDT (256KB)
 405  * f6f00000 - f7efffff     Sec OS image (16MB)
 406  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 407  */
 408 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
 409 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
 410 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
 411 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
 412 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 413 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 414
 415 #define CONFIG_PROG_UBOOT1                                              \
 416         "$download_cmd $loadaddr $ubootfile; "                          \
 417         "if test $? -eq 0; then "                                       \
 418                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 419                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 420                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 421                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 422                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 423                 "if test $? -ne 0; then "                               \
 424                         "echo PROGRAM FAILED; "                         \
 425                 "else; "                                                \
 426                         "echo PROGRAM SUCCEEDED; "                      \
 427                 "fi; "                                                  \
 428         "else; "                                                        \
 429                 "echo DOWNLOAD FAILED; "                                \
 430         "fi;"
 431
 432 #define CONFIG_PROG_UBOOT2                                              \
 433         "$download_cmd $loadaddr $ubootfile; "                          \
 434         "if test $? -eq 0; then "                                       \
 435                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 436                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 437                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 438                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 439                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 440                 "if test $? -ne 0; then "                               \
 441                         "echo PROGRAM FAILED; "                         \
 442                 "else; "                                                \
 443                         "echo PROGRAM SUCCEEDED; "                      \
 444                 "fi; "                                                  \
 445         "else; "                                                        \
 446                 "echo DOWNLOAD FAILED; "                                \
 447         "fi;"
 448
 449 #define CONFIG_BOOT_OS_NET                                              \
 450         "$download_cmd $osaddr $osfile; "                               \
 451         "if test $? -eq 0; then "                                       \
 452                 "if test -n $fdtaddr; then "                            \
 453                         "$download_cmd $fdtaddr $fdtfile; "             \
 454                         "if test $? -eq 0; then "                       \
 455                                 "bootm $osaddr - $fdtaddr; "            \
 456                         "else; "                                        \
 457                                 "echo FDT DOWNLOAD FAILED; "            \
 458                         "fi; "                                          \
 459                 "else; "                                                \
 460                         "bootm $osaddr; "                               \
 461                 "fi; "                                                  \
 462         "else; "                                                        \
 463                 "echo OS DOWNLOAD FAILED; "                             \
 464         "fi;"
 465
 466 #define CONFIG_PROG_OS1                                                 \
 467         "$download_cmd $osaddr $osfile; "                               \
 468         "if test $? -eq 0; then "                                       \
 469                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 470                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 471                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 472                 "if test $? -ne 0; then "                               \
 473                         "echo OS PROGRAM FAILED; "                      \
 474                 "else; "                                                \
 475                         "echo OS PROGRAM SUCCEEDED; "                   \
 476                 "fi; "                                                  \
 477         "else; "                                                        \
 478                 "echo OS DOWNLOAD FAILED; "                             \
 479         "fi;"
 480
 481 #define CONFIG_PROG_OS2                                                 \
 482         "$download_cmd $osaddr $osfile; "                               \
 483         "if test $? -eq 0; then "                                       \
 484                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 485                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 486                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 487                 "if test $? -ne 0; then "                               \
 488                         "echo OS PROGRAM FAILED; "                      \
 489                 "else; "                                                \
 490                         "echo OS PROGRAM SUCCEEDED; "                   \
 491                 "fi; "                                                  \
 492         "else; "                                                        \
 493                 "echo OS DOWNLOAD FAILED; "                             \
 494         "fi;"
 495
 496 #define CONFIG_PROG_FDT1                                                \
 497         "$download_cmd $fdtaddr $fdtfile; "                             \
 498         "if test $? -eq 0; then "                                       \
 499                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 500                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 501                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 502                 "if test $? -ne 0; then "                               \
 503                         "echo FDT PROGRAM FAILED; "                     \
 504                 "else; "                                                \
 505                         "echo FDT PROGRAM SUCCEEDED; "                  \
 506                 "fi; "                                                  \
 507         "else; "                                                        \
 508                 "echo FDT DOWNLOAD FAILED; "                            \
 509         "fi;"
 510
 511 #define CONFIG_PROG_FDT2                                                \
 512         "$download_cmd $fdtaddr $fdtfile; "                             \
 513         "if test $? -eq 0; then "                                       \
 514                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 515                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 516                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 517                 "if test $? -ne 0; then "                               \
 518                         "echo FDT PROGRAM FAILED; "                     \
 519                 "else; "                                                \
 520                         "echo FDT PROGRAM SUCCEEDED; "                  \
 521                 "fi; "                                                  \
 522         "else; "                                                        \
 523                 "echo FDT DOWNLOAD FAILED; "                            \
 524         "fi;"
 525
 526 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 527         "autoload=yes\0"                                                \
 528         "download_cmd=tftp\0"                                           \
 529         "console_args=console=ttyS0,115200\0"                           \
 530         "root_args=root=/dev/nfs rw\0"                                  \
 531         "misc_args=ip=on\0"                                             \
 532         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 533         "bootfile=/home/user/file\0"                                    \
 534         "osfile=/home/user/board.uImage\0"                              \
 535         "fdtfile=/home/user/board.dtb\0"                                \
 536         "ubootfile=/home/user/u-boot.bin\0"                             \
 537         "fdtaddr=0x1e00000\0"                                           \
 538         "osaddr=0x1000000\0"                                            \
 539         "loadaddr=0x1000000\0"                                          \
 540         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 541         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 542         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 543         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 544         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 545         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 546         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 547         "bootcmd_flash1=run set_bootargs; "                             \
 548                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 549         "bootcmd_flash2=run set_bootargs; "                             \
 550                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 551         "bootcmd=run bootcmd_flash1\0"
 552 #endif  /* __CONFIG_H */