Merge branch '2019-05-24-master-imports'
[platform/kernel/u-boot.git] / include / configs / xpedite550x.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2010 Extreme Engineering Solutions, Inc.
4  * Copyright 2007-2008 Freescale Semiconductor, Inc.
5  */
6
7 /*
8  * xpedite550x board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12
13 /*
14  * High Level Configuration Options
15  */
16 #define CONFIG_SYS_BOARD_NAME   "XPedite5500"
17 #define CONFIG_SYS_FORM_PMC_XMC 1
18 #define CONFIG_PRPMC_PCI_ALIAS  "pci0"  /* Processor PMC interface on pci0 */
19
20 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
21 #define CONFIG_PCIE1            1       /* PCIE controller 1 (PEX8112 or XMC) */
22 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
23 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
24 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
25 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
26
27 /*
28  * Multicore config
29  */
30 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
31 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
32
33 /*
34  * DDR config
35  */
36 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
37 #define CONFIG_DDR_SPD
38 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
39 #define SPD_EEPROM_ADDRESS                      0x54
40 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
41 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
42 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
43 #define CONFIG_DDR_ECC
44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
45 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
46 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
47 #define CONFIG_VERY_BIG_RAM
48
49 #ifndef __ASSEMBLY__
50 extern unsigned long get_board_sys_clk(unsigned long dummy);
51 extern unsigned long get_board_ddr_clk(unsigned long dummy);
52 #endif
53
54 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
55 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
56
57 /*
58  * These can be toggled for performance analysis, otherwise use default.
59  */
60 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
61 #define CONFIG_BTB                      /* toggle branch predition */
62 #define CONFIG_ENABLE_36BIT_PHYS        1
63
64 #define CONFIG_SYS_CCSRBAR              0xef000000
65 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
66
67 /*
68  * Diagnostics
69  */
70 #define CONFIG_SYS_MEMTEST_START        0x10000000
71 #define CONFIG_SYS_MEMTEST_END          0x20000000
72 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
73                                          CONFIG_SYS_POST_I2C)
74 #define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_EEPROM_ADDR,    \
75                                          CONFIG_SYS_I2C_LM75_ADDR,      \
76                                          CONFIG_SYS_I2C_LM90_ADDR,      \
77                                          CONFIG_SYS_I2C_PCA953X_ADDR0,  \
78                                          CONFIG_SYS_I2C_PCA953X_ADDR2,  \
79                                          CONFIG_SYS_I2C_PCA953X_ADDR3,  \
80                                          CONFIG_SYS_I2C_RTC_ADDR}
81
82 /*
83  * Memory map
84  * 0x0000_0000 0x7fff_ffff      DDR                     2G Cacheable
85  * 0x8000_0000 0xbfff_ffff      PCIe1 Mem               1G non-cacheable
86  * 0xe000_0000 0xe7ff_ffff      SRAM/SSRAM/L1 Cache     128M non-cacheable
87  * 0xe800_0000 0xe87f_ffff      PCIe1 IO                8M non-cacheable
88  * 0xee00_0000 0xee00_ffff      Boot page translation   4K non-cacheable
89  * 0xef00_0000 0xef0f_ffff      CCSR/IMMR               1M non-cacheable
90  * 0xef80_0000 0xef8f_ffff      NAND Flash              1M non-cacheable
91  * 0xf000_0000 0xf7ff_ffff      NOR Flash 2             128M non-cacheable
92  * 0xf800_0000 0xffff_ffff      NOR Flash 1             128M non-cacheable
93  */
94
95 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
96
97 /*
98  * NAND flash configuration
99  */
100 #define CONFIG_SYS_NAND_BASE            0xef800000
101 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
102 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
103                                          CONFIG_SYS_NAND_BASE2}
104 #define CONFIG_SYS_MAX_NAND_DEVICE      2
105 #define CONFIG_NAND_FSL_ELBC
106
107 /*
108  * NOR flash configuration
109  */
110 #define CONFIG_SYS_FLASH_BASE           0xf8000000
111 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
112 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
113 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
114 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
115 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
116 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
117 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
118                                                   {0xf7f40000, 0xc0000} }
119 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
120
121 /*
122  * Chip select configuration
123  */
124 /* NOR Flash 0 on CS0 */
125 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
126                                  BR_PS_16               | \
127                                  BR_V)
128 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
129                                  OR_GPCM_CSNT           | \
130                                  OR_GPCM_XACS           | \
131                                  OR_GPCM_ACS_DIV2       | \
132                                  OR_GPCM_SCY_8          | \
133                                  OR_GPCM_TRLX           | \
134                                  OR_GPCM_EHTR           | \
135                                  OR_GPCM_EAD)
136
137 /* NOR Flash 1 on CS1 */
138 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
139                                  BR_PS_16               | \
140                                  BR_V)
141 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
142
143 /* NAND flash on CS2 */
144 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
145                                  (2<<BR_DECC_SHIFT)     | \
146                                  BR_PS_8                | \
147                                  BR_MS_FCM              | \
148                                  BR_V)
149
150 /* NAND flash on CS2 */
151 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
152                                  OR_FCM_PGS     | \
153                                  OR_FCM_CSCT    | \
154                                  OR_FCM_CST     | \
155                                  OR_FCM_CHT     | \
156                                  OR_FCM_SCY_1   | \
157                                  OR_FCM_TRLX    | \
158                                  OR_FCM_EHTR)
159
160 /* NAND flash on CS3 */
161 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
162                                  (2<<BR_DECC_SHIFT)     | \
163                                  BR_PS_8                | \
164                                  BR_MS_FCM              | \
165                                  BR_V)
166 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
167
168 /*
169  * Use L1 as initial stack
170  */
171 #define CONFIG_SYS_INIT_RAM_LOCK        1
172 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
173 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
174
175 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
176 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
177
178 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
179 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
180
181 /*
182  * Serial Port
183  */
184 #define CONFIG_SYS_NS16550_SERIAL
185 #define CONFIG_SYS_NS16550_REG_SIZE     1
186 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
187 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
188 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
189 #define CONFIG_SYS_BAUDRATE_TABLE       \
190         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
191 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
192 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
193
194
195 /*
196  * I2C
197  */
198 #define CONFIG_SYS_I2C
199 #define CONFIG_SYS_I2C_FSL
200 #define CONFIG_SYS_FSL_I2C_SPEED        400000
201 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
202 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
203 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
204 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
205 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
206
207 /* I2C DS7505 temperature sensor */
208 #define CONFIG_SYS_I2C_LM75_ADDR        0x48
209
210 /* I2C ADT7461 temperature sensor */
211 #define CONFIG_SYS_I2C_LM90_ADDR        0x4C
212
213 /* I2C EEPROM - AT24C128B */
214 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
215 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
218
219 /* I2C RTC */
220 #define CONFIG_RTC_M41T11               1
221 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
222 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
223
224 /* GPIO */
225 #define CONFIG_PCA953X
226 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
227 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
228 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
229 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
230 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
231
232 /*
233  * GPIO pin definitions, PU = pulled high, PD = pulled low
234  */
235 /* PCA9557 @ 0x18*/
236 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
237 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
238 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
239 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
240 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
241 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Write protection (0: disabled, 1: enabled) */
242
243 /* PCA9557 @ 0x1e*/
244 #define CONFIG_SYS_PCA953X_XMC_GA0              0x01 /* PU; */
245 #define CONFIG_SYS_PCA953X_XMC_GA1              0x02 /* PU; */
246 #define CONFIG_SYS_PCA953X_XMC_GA2              0x04 /* PU; */
247 #define CONFIG_SYS_PCA953X_XMC_WAKE             0x10 /* PU; */
248 #define CONFIG_SYS_PCA953X_XMC_BIST             0x20 /* Enable XMC BIST */
249 #define CONFIG_SYS_PCA953X_PMC_EREADY           0x40 /* PU; PMC PCI eready */
250 #define CONFIG_SYS_PCA953X_PMC_MONARCH          0x80 /* PMC monarch mode enable */
251
252 /* PCA9557 @ 0x1f */
253 #define CONFIG_SYS_PCA953X_MC_GPIO0             0x01 /* PU; */
254 #define CONFIG_SYS_PCA953X_MC_GPIO1             0x02 /* PU; */
255 #define CONFIG_SYS_PCA953X_MC_GPIO2             0x04 /* PU; */
256 #define CONFIG_SYS_PCA953X_MC_GPIO3             0x08 /* PU; */
257 #define CONFIG_SYS_PCA953X_MC_GPIO4             0x10 /* PU; */
258 #define CONFIG_SYS_PCA953X_MC_GPIO5             0x20 /* PU; */
259 #define CONFIG_SYS_PCA953X_MC_GPIO6             0x40 /* PU; */
260 #define CONFIG_SYS_PCA953X_MC_GPIO7             0x80 /* PU; */
261
262 /*
263  * General PCI
264  * Memory space is mapped 1-1, but I/O space must start from 0.
265  */
266
267 /* controller 1 - PEX8112 or XMC, depending on build option */
268 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
269 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
270 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
271 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
272 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
273 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
274
275 /*
276  * Networking options
277  */
278 #define CONFIG_TSEC_TBI
279 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
280 #define CONFIG_ETHPRIME         "eTSEC2"
281
282 /*
283  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
284  * 1000mbps SGMII link
285  */
286 #define CONFIG_TSEC_TBICR_SETTINGS ( \
287                 TBICR_PHY_RESET \
288                 | TBICR_FULL_DUPLEX \
289                 | TBICR_SPEED1_SET \
290                 )
291
292 #define CONFIG_TSEC1            1
293 #define CONFIG_TSEC1_NAME       "eTSEC1"
294 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
295 #define TSEC1_PHY_ADDR          1
296 #define TSEC1_PHYIDX            0
297 #define CONFIG_HAS_ETH0
298
299 #define CONFIG_TSEC2            1
300 #define CONFIG_TSEC2_NAME       "eTSEC2"
301 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
302 #define TSEC2_PHY_ADDR          2
303 #define TSEC2_PHYIDX            0
304 #define CONFIG_HAS_ETH1
305
306 #define CONFIG_TSEC3            1
307 #define CONFIG_TSEC3_NAME       "eTSEC3"
308 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
309 #define TSEC3_PHY_ADDR          3
310 #define TSEC3_PHYIDX            0
311 #define CONFIG_HAS_ETH2
312
313 /*
314  * USB
315  */
316 #define CONFIG_USB_EHCI_FSL
317 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
318
319 /*
320  * Miscellaneous configurable options
321  */
322 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
323 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
324 #define CONFIG_PREBOOT                          /* enable preboot variable */
325 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
326
327 /*
328  * For booting Linux, the board info and command line data
329  * have to be in the first 16 MB of memory, since this is
330  * the maximum mapped by the Linux kernel during initialization.
331  */
332 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
333 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
334
335 /*
336  * Environment Configuration
337  */
338 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
339 #define CONFIG_ENV_SIZE         0x8000
340 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
341
342 /*
343  * Flash memory map:
344  * fff80000 - ffffffff     Pri U-Boot (512 KB)
345  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
346  * fff00000 - fff3ffff     Pri FDT (256KB)
347  * fef00000 - ffefffff     Pri OS image (16MB)
348  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
349  *
350  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
351  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
352  * f7f00000 - f7f3ffff     Sec FDT (256KB)
353  * f6f00000 - f7efffff     Sec OS image (16MB)
354  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
355  */
356 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
357 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
358 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
359 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
360 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
361 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
362
363 #define CONFIG_PROG_UBOOT1                                              \
364         "$download_cmd $loadaddr $ubootfile; "                          \
365         "if test $? -eq 0; then "                                       \
366                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
367                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
368                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
369                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
370                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
371                 "if test $? -ne 0; then "                               \
372                         "echo PROGRAM FAILED; "                         \
373                 "else; "                                                \
374                         "echo PROGRAM SUCCEEDED; "                      \
375                 "fi; "                                                  \
376         "else; "                                                        \
377                 "echo DOWNLOAD FAILED; "                                \
378         "fi;"
379
380 #define CONFIG_PROG_UBOOT2                                              \
381         "$download_cmd $loadaddr $ubootfile; "                          \
382         "if test $? -eq 0; then "                                       \
383                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
384                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
385                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
386                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
387                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
388                 "if test $? -ne 0; then "                               \
389                         "echo PROGRAM FAILED; "                         \
390                 "else; "                                                \
391                         "echo PROGRAM SUCCEEDED; "                      \
392                 "fi; "                                                  \
393         "else; "                                                        \
394                 "echo DOWNLOAD FAILED; "                                \
395         "fi;"
396
397 #define CONFIG_BOOT_OS_NET                                              \
398         "$download_cmd $osaddr $osfile; "                               \
399         "if test $? -eq 0; then "                                       \
400                 "if test -n $fdtaddr; then "                            \
401                         "$download_cmd $fdtaddr $fdtfile; "             \
402                         "if test $? -eq 0; then "                       \
403                                 "bootm $osaddr - $fdtaddr; "            \
404                         "else; "                                        \
405                                 "echo FDT DOWNLOAD FAILED; "            \
406                         "fi; "                                          \
407                 "else; "                                                \
408                         "bootm $osaddr; "                               \
409                 "fi; "                                                  \
410         "else; "                                                        \
411                 "echo OS DOWNLOAD FAILED; "                             \
412         "fi;"
413
414 #define CONFIG_PROG_OS1                                                 \
415         "$download_cmd $osaddr $osfile; "                               \
416         "if test $? -eq 0; then "                                       \
417                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
418                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
419                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
420                 "if test $? -ne 0; then "                               \
421                         "echo OS PROGRAM FAILED; "                      \
422                 "else; "                                                \
423                         "echo OS PROGRAM SUCCEEDED; "                   \
424                 "fi; "                                                  \
425         "else; "                                                        \
426                 "echo OS DOWNLOAD FAILED; "                             \
427         "fi;"
428
429 #define CONFIG_PROG_OS2                                                 \
430         "$download_cmd $osaddr $osfile; "                               \
431         "if test $? -eq 0; then "                                       \
432                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
433                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
434                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
435                 "if test $? -ne 0; then "                               \
436                         "echo OS PROGRAM FAILED; "                      \
437                 "else; "                                                \
438                         "echo OS PROGRAM SUCCEEDED; "                   \
439                 "fi; "                                                  \
440         "else; "                                                        \
441                 "echo OS DOWNLOAD FAILED; "                             \
442         "fi;"
443
444 #define CONFIG_PROG_FDT1                                                \
445         "$download_cmd $fdtaddr $fdtfile; "                             \
446         "if test $? -eq 0; then "                                       \
447                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
448                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
449                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
450                 "if test $? -ne 0; then "                               \
451                         "echo FDT PROGRAM FAILED; "                     \
452                 "else; "                                                \
453                         "echo FDT PROGRAM SUCCEEDED; "                  \
454                 "fi; "                                                  \
455         "else; "                                                        \
456                 "echo FDT DOWNLOAD FAILED; "                            \
457         "fi;"
458
459 #define CONFIG_PROG_FDT2                                                \
460         "$download_cmd $fdtaddr $fdtfile; "                             \
461         "if test $? -eq 0; then "                                       \
462                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
463                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
464                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
465                 "if test $? -ne 0; then "                               \
466                         "echo FDT PROGRAM FAILED; "                     \
467                 "else; "                                                \
468                         "echo FDT PROGRAM SUCCEEDED; "                  \
469                 "fi; "                                                  \
470         "else; "                                                        \
471                 "echo FDT DOWNLOAD FAILED; "                            \
472         "fi;"
473
474 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
475         "autoload=yes\0"                                                \
476         "download_cmd=tftp\0"                                           \
477         "console_args=console=ttyS0,115200\0"                           \
478         "root_args=root=/dev/nfs rw\0"                                  \
479         "misc_args=ip=on\0"                                             \
480         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
481         "bootfile=/home/user/file\0"                                    \
482         "osfile=/home/user/board.uImage\0"                              \
483         "fdtfile=/home/user/board.dtb\0"                                \
484         "ubootfile=/home/user/u-boot.bin\0"                             \
485         "fdtaddr=0x1e00000\0"                                           \
486         "osaddr=0x1000000\0"                                            \
487         "loadaddr=0x1000000\0"                                          \
488         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
489         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
490         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
491         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
492         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
493         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
494         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
495         "bootcmd_flash1=run set_bootargs; "                             \
496                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
497         "bootcmd_flash2=run set_bootargs; "                             \
498                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
499         "bootcmd=run bootcmd_flash1\0"
500 #endif  /* __CONFIG_H */