include/configs/xpedite537x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2008 Extreme Engineering Solutions, Inc.
   4  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   5  */
   6
   7 /*
   8  * xpedite537x board configuration file
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_SYS_BOARD_NAME   "XPedite5370"
  17 #define CONFIG_SYS_FORM_3U_VPX  1
  18
  19 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  20 #define CONFIG_PCIE1            1       /* PCIE controller 1 */
  21 #define CONFIG_PCIE2            1       /* PCIE controller 2 */
  22 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  23 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  24 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  25
  26 /*
  27  * Multicore config
  28  */
  29 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  30 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  31
  32 /*
  33  * DDR config
  34  */
  35 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  36 #define CONFIG_DDR_SPD
  37 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  38 #define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
  39 #define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
  40 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  41 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  42 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  43 #define CONFIG_DDR_ECC
  44 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  45 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  46 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  47 #define CONFIG_VERY_BIG_RAM
  48
  49 #ifndef __ASSEMBLY__
  50 extern unsigned long get_board_sys_clk(unsigned long dummy);
  51 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  52 #endif
  53
  54 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  55 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  56
  57 /*
  58  * These can be toggled for performance analysis, otherwise use default.
  59  */
  60 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  61 #define CONFIG_BTB                      /* toggle branch predition */
  62 #define CONFIG_ENABLE_36BIT_PHYS        1
  63
  64 #define CONFIG_SYS_CCSRBAR              0xef000000
  65 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  66
  67 /*
  68  * Diagnostics
  69  */
  70 #define CONFIG_SYS_MEMTEST_START        0x10000000
  71 #define CONFIG_SYS_MEMTEST_END          0x20000000
  72 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
  73                                          CONFIG_SYS_POST_I2C)
  74 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
  75 #define I2C_ADDR_IGNORE_LIST            {0x50}
  76
  77 /*
  78  * Memory map
  79  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
  80  * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
  81  * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
  82  * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
  83  * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
  84  * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
  85  * 0xee00_0000  0xee00_ffff     Boot page translation   4K non-cacheable
  86  * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
  87  * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
  88  * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
  89  * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
  90  */
  91
  92 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
  93
  94 /*
  95  * NAND flash configuration
  96  */
  97 #define CONFIG_SYS_NAND_BASE            0xef800000
  98 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
  99 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
 100                                          CONFIG_SYS_NAND_BASE2}
 101 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 102 #define CONFIG_NAND_FSL_ELBC
 103
 104 /*
 105  * NOR flash configuration
 106  */
 107 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 108 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 109 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 110 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 111 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 112 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 113 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 114 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 115                                                   {0xf7f40000, 0xc0000} }
 116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 117
 118 /*
 119  * Chip select configuration
 120  */
 121 /* NOR Flash 0 on CS0 */
 122 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 123                                  BR_PS_16               | \
 124                                  BR_V)
 125 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 126                                  OR_GPCM_CSNT           | \
 127                                  OR_GPCM_XACS           | \
 128                                  OR_GPCM_ACS_DIV2       | \
 129                                  OR_GPCM_SCY_8          | \
 130                                  OR_GPCM_TRLX           | \
 131                                  OR_GPCM_EHTR           | \
 132                                  OR_GPCM_EAD)
 133
 134 /* NOR Flash 1 on CS1 */
 135 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 136                                  BR_PS_16               | \
 137                                  BR_V)
 138 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 139
 140 /* NAND flash on CS2 */
 141 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 142                                  (2<<BR_DECC_SHIFT)     | \
 143                                  BR_PS_8                | \
 144                                  BR_MS_FCM              | \
 145                                  BR_V)
 146
 147 /* NAND flash on CS2 */
 148 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 149                                  OR_FCM_PGS     | \
 150                                  OR_FCM_CSCT    | \
 151                                  OR_FCM_CST     | \
 152                                  OR_FCM_CHT     | \
 153                                  OR_FCM_SCY_1   | \
 154                                  OR_FCM_TRLX    | \
 155                                  OR_FCM_EHTR)
 156
 157 /* NAND flash on CS3 */
 158 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 159                                  (2<<BR_DECC_SHIFT)     | \
 160                                  BR_PS_8                | \
 161                                  BR_MS_FCM              | \
 162                                  BR_V)
 163 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 164
 165 /*
 166  * Use L1 as initial stack
 167  */
 168 #define CONFIG_SYS_INIT_RAM_LOCK        1
 169 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 170 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 171
 172 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 173 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 174
 175 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 176 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 177
 178 /*
 179  * Serial Port
 180  */
 181 #define CONFIG_SYS_NS16550_SERIAL
 182 #define CONFIG_SYS_NS16550_REG_SIZE     1
 183 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 184 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 185 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 186 #define CONFIG_SYS_BAUDRATE_TABLE       \
 187         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 188 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 189 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 190
 191 /*
 192  * I2C
 193  */
 194 #define CONFIG_SYS_I2C
 195 #define CONFIG_SYS_I2C_FSL
 196 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 197 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 198 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 199 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 200 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 201 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 202 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 203
 204 /* PEX8518 slave I2C interface */
 205 #define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
 206
 207 /* I2C DS1631 temperature sensor */
 208 #define CONFIG_SYS_I2C_LM90_ADDR        0x4c
 209
 210 /* I2C EEPROM - AT24C128B */
 211 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 212 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 213 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 215
 216 /* I2C RTC */
 217 #define CONFIG_RTC_M41T11               1
 218 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 219 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 220
 221 /* GPIO */
 222 #define CONFIG_PCA953X
 223 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 224 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 225 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 226 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 227 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 228
 229 /*
 230  * PU = pulled high, PD = pulled low
 231  * I = input, O = output, IO = input/output
 232  */
 233 /* PCA9557 @ 0x18*/
 234 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 235 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
 236 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 237 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
 238 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 239 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
 240 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2        0x40 /* VID2 of ISL6262 */
 241 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3        0x80 /* VID3 of ISL6262 */
 242
 243 /* PCA9557 @ 0x1c*/
 244 #define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
 245 #define CONFIG_SYS_PCA953X_XMC0_MVMR0           0x02 /* XMC EEPROM write protect */
 246 #define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
 247 #define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
 248 #define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
 249 #define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
 250 #define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
 251 #define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
 252
 253 /* PCA9557 @ 0x1e*/
 254 #define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
 255 #define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
 256 #define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
 257 #define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
 258 #define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
 259 #define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; tied to VPX P0.GAP */
 260 #define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
 261
 262 /* PCA9557 @ 0x1f */
 263 #define CONFIG_SYS_PCA953X_GPIO_VPX0            0x01 /* PU */
 264 #define CONFIG_SYS_PCA953X_GPIO_VPX1            0x02 /* PU */
 265 #define CONFIG_SYS_PCA953X_GPIO_VPX2            0x04 /* PU */
 266 #define CONFIG_SYS_PCA953X_GPIO_VPX3            0x08 /* PU */
 267 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL        0x10 /* PD; I2C master source for FRU SEEPROM */
 268
 269 /*
 270  * General PCI
 271  * Memory space is mapped 1-1, but I/O space must start from 0.
 272  */
 273 /* PCIE1 - VPX P1 */
 274 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 275 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 276 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 277 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 278 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 279 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 280
 281 /* PCIE2 - PEX8518 */
 282 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
 283 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 284 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 285 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 286 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
 287 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
 288
 289 /*
 290  * Networking options
 291  */
 292 #define CONFIG_TSEC_TBI
 293 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 294 #define CONFIG_ETHPRIME         "eTSEC2"
 295
 296 /*
 297  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 298  * 1000mbps SGMII link
 299  */
 300 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 301                 TBICR_PHY_RESET \
 302                 | TBICR_FULL_DUPLEX \
 303                 | TBICR_SPEED1_SET \
 304                 )
 305
 306 #define CONFIG_TSEC1            1
 307 #define CONFIG_TSEC1_NAME       "eTSEC1"
 308 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 309 #define TSEC1_PHY_ADDR          1
 310 #define TSEC1_PHYIDX            0
 311 #define CONFIG_HAS_ETH0
 312
 313 #define CONFIG_TSEC2            1
 314 #define CONFIG_TSEC2_NAME       "eTSEC2"
 315 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 316 #define TSEC2_PHY_ADDR          2
 317 #define TSEC2_PHYIDX            0
 318 #define CONFIG_HAS_ETH1
 319
 320 /*
 321  * Miscellaneous configurable options
 322  */
 323 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 324 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 325 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 326
 327 /*
 328  * For booting Linux, the board info and command line data
 329  * have to be in the first 16 MB of memory, since this is
 330  * the maximum mapped by the Linux kernel during initialization.
 331  */
 332 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 333 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 334
 335 /*
 336  * Environment Configuration
 337  */
 338
 339 /*
 340  * Flash memory map:
 341  * fff80000 - ffffffff     Pri U-Boot (512 KB)
 342  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 343  * fff00000 - fff3ffff     Pri FDT (256KB)
 344  * fef00000 - ffefffff     Pri OS image (16MB)
 345  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 346  *
 347  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 348  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 349  * f7f00000 - f7f3ffff     Sec FDT (256KB)
 350  * f6f00000 - f7efffff     Sec OS image (16MB)
 351  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 352  */
 353 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
 354 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
 355 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
 356 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
 357 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 358 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 359
 360 #define CONFIG_PROG_UBOOT1                                              \
 361         "$download_cmd $loadaddr $ubootfile; "                          \
 362         "if test $? -eq 0; then "                                       \
 363                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 364                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 365                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 366                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 367                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 368                 "if test $? -ne 0; then "                               \
 369                         "echo PROGRAM FAILED; "                         \
 370                 "else; "                                                \
 371                         "echo PROGRAM SUCCEEDED; "                      \
 372                 "fi; "                                                  \
 373         "else; "                                                        \
 374                 "echo DOWNLOAD FAILED; "                                \
 375         "fi;"
 376
 377 #define CONFIG_PROG_UBOOT2                                              \
 378         "$download_cmd $loadaddr $ubootfile; "                          \
 379         "if test $? -eq 0; then "                                       \
 380                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 381                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 382                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 383                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 384                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 385                 "if test $? -ne 0; then "                               \
 386                         "echo PROGRAM FAILED; "                         \
 387                 "else; "                                                \
 388                         "echo PROGRAM SUCCEEDED; "                      \
 389                 "fi; "                                                  \
 390         "else; "                                                        \
 391                 "echo DOWNLOAD FAILED; "                                \
 392         "fi;"
 393
 394 #define CONFIG_BOOT_OS_NET                                              \
 395         "$download_cmd $osaddr $osfile; "                               \
 396         "if test $? -eq 0; then "                                       \
 397                 "if test -n $fdtaddr; then "                            \
 398                         "$download_cmd $fdtaddr $fdtfile; "             \
 399                         "if test $? -eq 0; then "                       \
 400                                 "bootm $osaddr - $fdtaddr; "            \
 401                         "else; "                                        \
 402                                 "echo FDT DOWNLOAD FAILED; "            \
 403                         "fi; "                                          \
 404                 "else; "                                                \
 405                         "bootm $osaddr; "                               \
 406                 "fi; "                                                  \
 407         "else; "                                                        \
 408                 "echo OS DOWNLOAD FAILED; "                             \
 409         "fi;"
 410
 411 #define CONFIG_PROG_OS1                                                 \
 412         "$download_cmd $osaddr $osfile; "                               \
 413         "if test $? -eq 0; then "                                       \
 414                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 415                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 416                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 417                 "if test $? -ne 0; then "                               \
 418                         "echo OS PROGRAM FAILED; "                      \
 419                 "else; "                                                \
 420                         "echo OS PROGRAM SUCCEEDED; "                   \
 421                 "fi; "                                                  \
 422         "else; "                                                        \
 423                 "echo OS DOWNLOAD FAILED; "                             \
 424         "fi;"
 425
 426 #define CONFIG_PROG_OS2                                                 \
 427         "$download_cmd $osaddr $osfile; "                               \
 428         "if test $? -eq 0; then "                                       \
 429                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 430                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 431                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 432                 "if test $? -ne 0; then "                               \
 433                         "echo OS PROGRAM FAILED; "                      \
 434                 "else; "                                                \
 435                         "echo OS PROGRAM SUCCEEDED; "                   \
 436                 "fi; "                                                  \
 437         "else; "                                                        \
 438                 "echo OS DOWNLOAD FAILED; "                             \
 439         "fi;"
 440
 441 #define CONFIG_PROG_FDT1                                                \
 442         "$download_cmd $fdtaddr $fdtfile; "                             \
 443         "if test $? -eq 0; then "                                       \
 444                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 445                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 446                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 447                 "if test $? -ne 0; then "                               \
 448                         "echo FDT PROGRAM FAILED; "                     \
 449                 "else; "                                                \
 450                         "echo FDT PROGRAM SUCCEEDED; "                  \
 451                 "fi; "                                                  \
 452         "else; "                                                        \
 453                 "echo FDT DOWNLOAD FAILED; "                            \
 454         "fi;"
 455
 456 #define CONFIG_PROG_FDT2                                                \
 457         "$download_cmd $fdtaddr $fdtfile; "                             \
 458         "if test $? -eq 0; then "                                       \
 459                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 460                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 461                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 462                 "if test $? -ne 0; then "                               \
 463                         "echo FDT PROGRAM FAILED; "                     \
 464                 "else; "                                                \
 465                         "echo FDT PROGRAM SUCCEEDED; "                  \
 466                 "fi; "                                                  \
 467         "else; "                                                        \
 468                 "echo FDT DOWNLOAD FAILED; "                            \
 469         "fi;"
 470
 471 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 472         "autoload=yes\0"                                                \
 473         "download_cmd=tftp\0"                                           \
 474         "console_args=console=ttyS0,115200\0"                           \
 475         "root_args=root=/dev/nfs rw\0"                                  \
 476         "misc_args=ip=on\0"                                             \
 477         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 478         "bootfile=/home/user/file\0"                                    \
 479         "osfile=/home/user/board.uImage\0"                              \
 480         "fdtfile=/home/user/board.dtb\0"                                \
 481         "ubootfile=/home/user/u-boot.bin\0"                             \
 482         "fdtaddr=0x1e00000\0"                                           \
 483         "osaddr=0x1000000\0"                                            \
 484         "loadaddr=0x1000000\0"                                          \
 485         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 486         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 487         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 488         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 489         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 490         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 491         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 492         "bootcmd_flash1=run set_bootargs; "                             \
 493                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 494         "bootcmd_flash2=run set_bootargs; "                             \
 495                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 496         "bootcmd=run bootcmd_flash1\0"
 497 #endif  /* __CONFIG_H */