1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2008 Extreme Engineering Solutions, Inc.
4 * Copyright 2004-2008 Freescale Semiconductor, Inc.
8 * xpedite520x board configuration file
14 * High Level Configuration Options
16 #define CONFIG_SYS_BOARD_NAME "XPedite5200"
17 #define CONFIG_SYS_FORM_PMC_XMC 1
19 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
20 #define CONFIG_PCI1 1 /* PCI controller 1 */
21 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
22 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
23 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
28 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
29 #define CONFIG_DDR_SPD
30 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
31 #define SPD_EEPROM_ADDRESS 0x54
32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
33 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
34 #define CONFIG_DDR_ECC
35 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
36 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
37 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
38 #define CONFIG_VERY_BIG_RAM
40 #define CONFIG_SYS_CLK_FREQ 66666666
43 * These can be toggled for performance analysis, otherwise use default.
45 #define CONFIG_L2_CACHE /* toggle L2 cache */
46 #define CONFIG_BTB /* toggle branch predition */
47 #define CONFIG_ENABLE_36BIT_PHYS 1
49 #define CONFIG_SYS_CCSRBAR 0xef000000
50 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
55 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
57 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
58 CONFIG_SYS_I2C_EEPROM_ADDR, \
59 CONFIG_SYS_I2C_PCA953X_ADDR0, \
60 CONFIG_SYS_I2C_PCA953X_ADDR1, \
61 CONFIG_SYS_I2C_RTC_ADDR}
65 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
66 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
67 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
68 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
69 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
70 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
71 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
72 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
75 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
78 * NAND flash configuration
80 #define CONFIG_SYS_NAND_BASE 0xef800000
81 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
82 #define CONFIG_SYS_MAX_NAND_DEVICE 1
83 #define CONFIG_NAND_ACTL
84 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
85 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
86 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
87 #define CONFIG_SYS_NAND_ACTL_DELAY 25
90 * NOR flash configuration
92 #define CONFIG_SYS_FLASH_BASE 0xfc000000
93 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
94 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
95 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
96 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
97 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
98 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
99 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
100 {0xfbf40000, 0xc0000} }
101 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
104 * Chip select configuration
106 /* NOR Flash 0 on CS0 */
107 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
110 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
114 /* NOR Flash 1 on CS1 */
115 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
118 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
120 /* NAND flash on CS2 */
121 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
125 /* NAND flash on CS2 */
126 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
134 /* NAND flash on CS3 */
135 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
138 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
141 * Use L1 as initial stack
143 #define CONFIG_SYS_INIT_RAM_LOCK 1
144 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
145 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
147 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
148 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
150 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
151 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
156 #define CONFIG_SYS_NS16550_SERIAL
157 #define CONFIG_SYS_NS16550_REG_SIZE 1
158 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
159 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
160 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
161 #define CONFIG_SYS_BAUDRATE_TABLE \
162 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
163 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
164 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
169 #define CONFIG_SYS_I2C
170 #define CONFIG_SYS_I2C_FSL
171 #define CONFIG_SYS_FSL_I2C_SPEED 400000
172 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
173 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
174 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
175 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
176 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
179 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
180 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
182 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
185 #define CONFIG_RTC_M41T11 1
186 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
187 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
190 #define CONFIG_PCA953X
191 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
192 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
193 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
196 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
197 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
198 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
199 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
200 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
201 #define CONFIG_SYS_PCA953X_NVM_WP 0x20
202 #define CONFIG_SYS_PCA953X_MONARCH 0x40
203 #define CONFIG_SYS_PCA953X_EREADY 0x80
206 #define CONFIG_SYS_PCA953X_P14_IO0 0x01
207 #define CONFIG_SYS_PCA953X_P14_IO1 0x02
208 #define CONFIG_SYS_PCA953X_P14_IO2 0x04
209 #define CONFIG_SYS_PCA953X_P14_IO3 0x08
210 #define CONFIG_SYS_PCA953X_P14_IO4 0x10
211 #define CONFIG_SYS_PCA953X_P14_IO5 0x20
212 #define CONFIG_SYS_PCA953X_P14_IO6 0x40
213 #define CONFIG_SYS_PCA953X_P14_IO7 0x80
215 /* 12-bit ADC used to measure CPU diode */
216 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
220 * Memory space is mapped 1-1, but I/O space must start from 0.
222 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
223 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
224 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
225 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
226 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
227 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
232 #define CONFIG_ETHPRIME "eTSEC1"
234 #define CONFIG_TSEC1 1
235 #define CONFIG_TSEC1_NAME "eTSEC1"
236 #define TSEC1_FLAGS TSEC_GIGABIT
237 #define TSEC1_PHY_ADDR 1
238 #define TSEC1_PHYIDX 0
239 #define CONFIG_HAS_ETH0
241 #define CONFIG_TSEC2 1
242 #define CONFIG_TSEC2_NAME "eTSEC2"
243 #define TSEC2_FLAGS TSEC_GIGABIT
244 #define TSEC2_PHY_ADDR 2
245 #define TSEC2_PHYIDX 0
246 #define CONFIG_HAS_ETH1
248 #define CONFIG_TSEC3 1
249 #define CONFIG_TSEC3_NAME "eTSEC3"
250 #define TSEC3_FLAGS TSEC_GIGABIT
251 #define TSEC3_PHY_ADDR 3
252 #define TSEC3_PHYIDX 0
253 #define CONFIG_HAS_ETH2
255 #define CONFIG_TSEC4 1
256 #define CONFIG_TSEC4_NAME "eTSEC4"
257 #define TSEC4_FLAGS TSEC_GIGABIT
258 #define TSEC4_PHY_ADDR 4
259 #define TSEC4_PHYIDX 0
260 #define CONFIG_HAS_ETH3
265 #define CONFIG_BOOTP_BOOTFILESIZE
268 * Miscellaneous configurable options
270 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
271 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
272 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
273 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
276 * For booting Linux, the board info and command line data
277 * have to be in the first 16 MB of memory, since this is
278 * the maximum mapped by the Linux kernel during initialization.
280 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
281 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
284 * Environment Configuration
289 * fff80000 - ffffffff Pri U-Boot (512 KB)
290 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
291 * fff00000 - fff3ffff Pri FDT (256KB)
292 * fef00000 - ffefffff Pri OS image (16MB)
293 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
295 * fbf80000 - fbffffff Sec U-Boot (512 KB)
296 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
297 * fbf00000 - fbf3ffff Sec FDT (256KB)
298 * faf00000 - fbefffff Sec OS image (16MB)
299 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
301 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
302 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
303 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
304 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
305 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
306 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
308 #define CONFIG_PROG_UBOOT1 \
309 "$download_cmd $loadaddr $ubootfile; " \
310 "if test $? -eq 0; then " \
311 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
312 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
313 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
314 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
315 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
316 "if test $? -ne 0; then " \
317 "echo PROGRAM FAILED; " \
319 "echo PROGRAM SUCCEEDED; " \
322 "echo DOWNLOAD FAILED; " \
325 #define CONFIG_PROG_UBOOT2 \
326 "$download_cmd $loadaddr $ubootfile; " \
327 "if test $? -eq 0; then " \
328 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
329 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
330 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
331 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
332 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
333 "if test $? -ne 0; then " \
334 "echo PROGRAM FAILED; " \
336 "echo PROGRAM SUCCEEDED; " \
339 "echo DOWNLOAD FAILED; " \
342 #define CONFIG_BOOT_OS_NET \
343 "$download_cmd $osaddr $osfile; " \
344 "if test $? -eq 0; then " \
345 "if test -n $fdtaddr; then " \
346 "$download_cmd $fdtaddr $fdtfile; " \
347 "if test $? -eq 0; then " \
348 "bootm $osaddr - $fdtaddr; " \
350 "echo FDT DOWNLOAD FAILED; " \
356 "echo OS DOWNLOAD FAILED; " \
359 #define CONFIG_PROG_OS1 \
360 "$download_cmd $osaddr $osfile; " \
361 "if test $? -eq 0; then " \
362 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
363 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
364 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
365 "if test $? -ne 0; then " \
366 "echo OS PROGRAM FAILED; " \
368 "echo OS PROGRAM SUCCEEDED; " \
371 "echo OS DOWNLOAD FAILED; " \
374 #define CONFIG_PROG_OS2 \
375 "$download_cmd $osaddr $osfile; " \
376 "if test $? -eq 0; then " \
377 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
378 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
379 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
380 "if test $? -ne 0; then " \
381 "echo OS PROGRAM FAILED; " \
383 "echo OS PROGRAM SUCCEEDED; " \
386 "echo OS DOWNLOAD FAILED; " \
389 #define CONFIG_PROG_FDT1 \
390 "$download_cmd $fdtaddr $fdtfile; " \
391 "if test $? -eq 0; then " \
392 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
393 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
394 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
395 "if test $? -ne 0; then " \
396 "echo FDT PROGRAM FAILED; " \
398 "echo FDT PROGRAM SUCCEEDED; " \
401 "echo FDT DOWNLOAD FAILED; " \
404 #define CONFIG_PROG_FDT2 \
405 "$download_cmd $fdtaddr $fdtfile; " \
406 "if test $? -eq 0; then " \
407 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
408 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
409 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
410 "if test $? -ne 0; then " \
411 "echo FDT PROGRAM FAILED; " \
413 "echo FDT PROGRAM SUCCEEDED; " \
416 "echo FDT DOWNLOAD FAILED; " \
419 #define CONFIG_EXTRA_ENV_SETTINGS \
421 "download_cmd=tftp\0" \
422 "console_args=console=ttyS0,115200\0" \
423 "root_args=root=/dev/nfs rw\0" \
424 "misc_args=ip=on\0" \
425 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
426 "bootfile=/home/user/file\0" \
427 "osfile=/home/user/board.uImage\0" \
428 "fdtfile=/home/user/board.dtb\0" \
429 "ubootfile=/home/user/u-boot.bin\0" \
430 "fdtaddr=0x1e00000\0" \
431 "osaddr=0x1000000\0" \
432 "loadaddr=0x1000000\0" \
433 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
434 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
435 "prog_os1="CONFIG_PROG_OS1"\0" \
436 "prog_os2="CONFIG_PROG_OS2"\0" \
437 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
438 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
439 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
440 "bootcmd_flash1=run set_bootargs; " \
441 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
442 "bootcmd_flash2=run set_bootargs; " \
443 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
444 "bootcmd=run bootcmd_flash1\0"
445 #endif /* __CONFIG_H */