2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 * xpedite520x board configuration file
15 * High Level Configuration Options
17 #define CONFIG_SYS_BOARD_NAME "XPedite5200"
18 #define CONFIG_SYS_FORM_PMC_XMC 1
19 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
21 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
22 #define CONFIG_PCI1 1 /* PCI controller 1 */
23 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
24 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
25 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
30 #undef CONFIG_FSL_DDR_INTERACTIVE
31 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
32 #define CONFIG_DDR_SPD
33 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
34 #define SPD_EEPROM_ADDRESS 0x54
35 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
36 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
37 #define CONFIG_DDR_ECC
38 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
39 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
40 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
41 #define CONFIG_VERY_BIG_RAM
43 #define CONFIG_SYS_CLK_FREQ 66666666
46 * These can be toggled for performance analysis, otherwise use default.
48 #define CONFIG_L2_CACHE /* toggle L2 cache */
49 #define CONFIG_BTB /* toggle branch predition */
50 #define CONFIG_ENABLE_36BIT_PHYS 1
52 #define CONFIG_SYS_CCSRBAR 0xef000000
53 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
58 #define CONFIG_SYS_ALT_MEMTEST
59 #define CONFIG_SYS_MEMTEST_START 0x10000000
60 #define CONFIG_SYS_MEMTEST_END 0x20000000
61 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
63 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
64 CONFIG_SYS_I2C_EEPROM_ADDR, \
65 CONFIG_SYS_I2C_PCA953X_ADDR0, \
66 CONFIG_SYS_I2C_PCA953X_ADDR1, \
67 CONFIG_SYS_I2C_RTC_ADDR}
71 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
72 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
73 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
74 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
75 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
76 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
77 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
78 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
81 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
84 * NAND flash configuration
86 #define CONFIG_SYS_NAND_BASE 0xef800000
87 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
88 #define CONFIG_SYS_MAX_NAND_DEVICE 1
89 #define CONFIG_NAND_ACTL
90 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
91 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
92 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
93 #define CONFIG_SYS_NAND_ACTL_DELAY 25
96 * NOR flash configuration
98 #define CONFIG_SYS_FLASH_BASE 0xfc000000
99 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
100 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
101 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
102 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
103 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
104 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
105 #define CONFIG_FLASH_CFI_DRIVER
106 #define CONFIG_SYS_FLASH_CFI
107 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
108 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
109 {0xfbf40000, 0xc0000} }
110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
113 * Chip select configuration
115 /* NOR Flash 0 on CS0 */
116 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
119 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
123 /* NOR Flash 1 on CS1 */
124 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
127 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
129 /* NAND flash on CS2 */
130 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
134 /* NAND flash on CS2 */
135 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
143 /* NAND flash on CS3 */
144 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
147 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
150 * Use L1 as initial stack
152 #define CONFIG_SYS_INIT_RAM_LOCK 1
153 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
154 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
156 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
157 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
159 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
160 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
165 #define CONFIG_CONS_INDEX 1
166 #define CONFIG_SYS_NS16550_SERIAL
167 #define CONFIG_SYS_NS16550_REG_SIZE 1
168 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
169 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
170 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
171 #define CONFIG_SYS_BAUDRATE_TABLE \
172 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
173 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
174 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
179 #define CONFIG_SYS_I2C
180 #define CONFIG_SYS_I2C_FSL
181 #define CONFIG_SYS_FSL_I2C_SPEED 400000
182 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
183 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
184 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
185 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
186 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
189 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
190 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
191 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
192 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
195 #define CONFIG_RTC_M41T11 1
196 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
197 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
200 #define CONFIG_PCA953X
201 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
202 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
203 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
206 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
207 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
208 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
209 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
210 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
211 #define CONFIG_SYS_PCA953X_NVM_WP 0x20
212 #define CONFIG_SYS_PCA953X_MONARCH 0x40
213 #define CONFIG_SYS_PCA953X_EREADY 0x80
216 #define CONFIG_SYS_PCA953X_P14_IO0 0x01
217 #define CONFIG_SYS_PCA953X_P14_IO1 0x02
218 #define CONFIG_SYS_PCA953X_P14_IO2 0x04
219 #define CONFIG_SYS_PCA953X_P14_IO3 0x08
220 #define CONFIG_SYS_PCA953X_P14_IO4 0x10
221 #define CONFIG_SYS_PCA953X_P14_IO5 0x20
222 #define CONFIG_SYS_PCA953X_P14_IO6 0x40
223 #define CONFIG_SYS_PCA953X_P14_IO7 0x80
225 /* 12-bit ADC used to measure CPU diode */
226 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
230 * Memory space is mapped 1-1, but I/O space must start from 0.
232 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
233 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
234 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
235 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
236 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
237 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
242 #define CONFIG_TSEC_ENET /* tsec ethernet support */
243 #define CONFIG_MII 1 /* MII PHY management */
244 #define CONFIG_ETHPRIME "eTSEC1"
246 #define CONFIG_TSEC1 1
247 #define CONFIG_TSEC1_NAME "eTSEC1"
248 #define TSEC1_FLAGS TSEC_GIGABIT
249 #define TSEC1_PHY_ADDR 1
250 #define TSEC1_PHYIDX 0
251 #define CONFIG_HAS_ETH0
253 #define CONFIG_TSEC2 1
254 #define CONFIG_TSEC2_NAME "eTSEC2"
255 #define TSEC2_FLAGS TSEC_GIGABIT
256 #define TSEC2_PHY_ADDR 2
257 #define TSEC2_PHYIDX 0
258 #define CONFIG_HAS_ETH1
260 #define CONFIG_TSEC3 1
261 #define CONFIG_TSEC3_NAME "eTSEC3"
262 #define TSEC3_FLAGS TSEC_GIGABIT
263 #define TSEC3_PHY_ADDR 3
264 #define TSEC3_PHYIDX 0
265 #define CONFIG_HAS_ETH2
267 #define CONFIG_TSEC4 1
268 #define CONFIG_TSEC4_NAME "eTSEC4"
269 #define TSEC4_FLAGS TSEC_GIGABIT
270 #define TSEC4_PHY_ADDR 4
271 #define TSEC4_PHYIDX 0
272 #define CONFIG_HAS_ETH3
277 #define CONFIG_BOOTP_BOOTFILESIZE
278 #define CONFIG_BOOTP_BOOTPATH
279 #define CONFIG_BOOTP_GATEWAY
282 * Miscellaneous configurable options
284 #define CONFIG_SYS_LONGHELP /* undef to save memory */
285 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
286 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
287 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
288 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
289 #define CONFIG_PREBOOT /* enable preboot variable */
290 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
291 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
294 * For booting Linux, the board info and command line data
295 * have to be in the first 16 MB of memory, since this is
296 * the maximum mapped by the Linux kernel during initialization.
298 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
299 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
302 * Environment Configuration
304 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
305 #define CONFIG_ENV_SIZE 0x8000
306 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
310 * fff80000 - ffffffff Pri U-Boot (512 KB)
311 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
312 * fff00000 - fff3ffff Pri FDT (256KB)
313 * fef00000 - ffefffff Pri OS image (16MB)
314 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
316 * fbf80000 - fbffffff Sec U-Boot (512 KB)
317 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
318 * fbf00000 - fbf3ffff Sec FDT (256KB)
319 * faf00000 - fbefffff Sec OS image (16MB)
320 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
322 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
323 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
324 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
325 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
326 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
327 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
329 #define CONFIG_PROG_UBOOT1 \
330 "$download_cmd $loadaddr $ubootfile; " \
331 "if test $? -eq 0; then " \
332 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
333 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
334 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
335 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
336 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
337 "if test $? -ne 0; then " \
338 "echo PROGRAM FAILED; " \
340 "echo PROGRAM SUCCEEDED; " \
343 "echo DOWNLOAD FAILED; " \
346 #define CONFIG_PROG_UBOOT2 \
347 "$download_cmd $loadaddr $ubootfile; " \
348 "if test $? -eq 0; then " \
349 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
350 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
351 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
352 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
353 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
354 "if test $? -ne 0; then " \
355 "echo PROGRAM FAILED; " \
357 "echo PROGRAM SUCCEEDED; " \
360 "echo DOWNLOAD FAILED; " \
363 #define CONFIG_BOOT_OS_NET \
364 "$download_cmd $osaddr $osfile; " \
365 "if test $? -eq 0; then " \
366 "if test -n $fdtaddr; then " \
367 "$download_cmd $fdtaddr $fdtfile; " \
368 "if test $? -eq 0; then " \
369 "bootm $osaddr - $fdtaddr; " \
371 "echo FDT DOWNLOAD FAILED; " \
377 "echo OS DOWNLOAD FAILED; " \
380 #define CONFIG_PROG_OS1 \
381 "$download_cmd $osaddr $osfile; " \
382 "if test $? -eq 0; then " \
383 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
384 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
385 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
386 "if test $? -ne 0; then " \
387 "echo OS PROGRAM FAILED; " \
389 "echo OS PROGRAM SUCCEEDED; " \
392 "echo OS DOWNLOAD FAILED; " \
395 #define CONFIG_PROG_OS2 \
396 "$download_cmd $osaddr $osfile; " \
397 "if test $? -eq 0; then " \
398 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
399 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
400 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
401 "if test $? -ne 0; then " \
402 "echo OS PROGRAM FAILED; " \
404 "echo OS PROGRAM SUCCEEDED; " \
407 "echo OS DOWNLOAD FAILED; " \
410 #define CONFIG_PROG_FDT1 \
411 "$download_cmd $fdtaddr $fdtfile; " \
412 "if test $? -eq 0; then " \
413 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
414 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
415 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
416 "if test $? -ne 0; then " \
417 "echo FDT PROGRAM FAILED; " \
419 "echo FDT PROGRAM SUCCEEDED; " \
422 "echo FDT DOWNLOAD FAILED; " \
425 #define CONFIG_PROG_FDT2 \
426 "$download_cmd $fdtaddr $fdtfile; " \
427 "if test $? -eq 0; then " \
428 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
429 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
430 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
431 "if test $? -ne 0; then " \
432 "echo FDT PROGRAM FAILED; " \
434 "echo FDT PROGRAM SUCCEEDED; " \
437 "echo FDT DOWNLOAD FAILED; " \
440 #define CONFIG_EXTRA_ENV_SETTINGS \
442 "download_cmd=tftp\0" \
443 "console_args=console=ttyS0,115200\0" \
444 "root_args=root=/dev/nfs rw\0" \
445 "misc_args=ip=on\0" \
446 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
447 "bootfile=/home/user/file\0" \
448 "osfile=/home/user/board.uImage\0" \
449 "fdtfile=/home/user/board.dtb\0" \
450 "ubootfile=/home/user/u-boot.bin\0" \
451 "fdtaddr=0x1e00000\0" \
452 "osaddr=0x1000000\0" \
453 "loadaddr=0x1000000\0" \
454 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
455 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
456 "prog_os1="CONFIG_PROG_OS1"\0" \
457 "prog_os2="CONFIG_PROG_OS2"\0" \
458 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
459 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
460 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
461 "bootcmd_flash1=run set_bootargs; " \
462 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
463 "bootcmd_flash2=run set_bootargs; " \
464 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
465 "bootcmd=run bootcmd_flash1\0"
466 #endif /* __CONFIG_H */