1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2009 Extreme Engineering Solutions, Inc.
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
8 * xpedite517x board configuration file
14 * High Level Configuration Options
16 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
17 #define CONFIG_SYS_FORM_3U_VPX 1
18 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
19 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
20 #define CONFIG_ALTIVEC 1
22 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
23 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
24 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
25 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
26 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
27 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
32 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
33 #define CONFIG_DDR_SPD
34 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
35 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
36 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
37 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
38 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
39 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
40 #define CONFIG_DDR_ECC
41 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
42 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
43 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
44 #define CONFIG_VERY_BIG_RAM
45 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
48 * virtual address to be used for temporary mappings. There
49 * should be 128k free at this VA.
51 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
54 #include <linux/stringify.h>
55 extern unsigned long get_board_sys_clk(unsigned long dummy);
58 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
65 #define L2_ENABLE (L2CR_L2E)
68 * Base addresses -- Note these are effective addresses where the
69 * actual resources get mapped (not physical addresses)
71 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
72 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
73 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
74 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
75 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
80 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
82 /* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
83 #define I2C_ADDR_IGNORE_LIST {0x50}
87 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
88 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
89 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
90 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
91 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
92 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
93 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
94 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
95 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
96 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
99 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
102 * NAND flash configuration
104 #define CONFIG_SYS_NAND_BASE 0xef800000
105 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
106 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
107 #define CONFIG_SYS_MAX_NAND_DEVICE 2
108 #define CONFIG_NAND_ACTL
109 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
110 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
111 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
112 #define CONFIG_SYS_NAND_ACTL_DELAY 25
113 #define CONFIG_JFFS2_NAND
116 * NOR flash configuration
118 #define CONFIG_SYS_FLASH_BASE 0xf8000000
119 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
120 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
121 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
122 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
123 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
124 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
125 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
126 {0xf7f00000, 0xc0000} }
127 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
128 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
131 * Chip select configuration
133 /* NOR Flash 0 on CS0 */
134 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
137 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
146 /* NOR Flash 1 on CS1 */
147 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
150 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
152 /* NAND flash on CS2 */
153 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
156 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
164 /* Optional NAND flash on CS3 */
165 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
168 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
171 * Use L1 as initial stack
173 #define CONFIG_SYS_INIT_RAM_LOCK 1
174 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
175 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
177 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
178 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
180 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
181 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
186 #define CONFIG_SYS_NS16550_SERIAL
187 #define CONFIG_SYS_NS16550_REG_SIZE 1
188 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
189 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
190 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
191 #define CONFIG_SYS_BAUDRATE_TABLE \
192 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
193 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
194 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
199 #define CONFIG_SYS_I2C
200 #define CONFIG_SYS_I2C_FSL
201 #define CONFIG_SYS_FSL_I2C_SPEED 100000
202 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
203 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
204 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
205 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
206 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
208 /* PEX8518 slave I2C interface */
209 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
211 /* I2C DS1631 temperature sensor */
212 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
214 /* I2C EEPROM - AT24C128B */
215 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
216 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
218 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
221 #define CONFIG_RTC_M41T11 1
222 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
223 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
226 #define CONFIG_PCA953X
227 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
228 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
229 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
230 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
231 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
232 #define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
235 * PU = pulled high, PD = pulled low
236 * I = input, O = output, IO = input/output
239 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
240 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
241 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
242 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
243 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
244 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
247 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
248 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
249 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
250 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
251 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
252 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
253 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
254 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
257 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
258 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
259 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
260 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
261 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
262 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
263 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
266 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
267 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
268 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
269 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
273 * Memory space is mapped 1-1, but I/O space must start from 0.
275 /* PCIE1 - PEX8518 */
276 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
277 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
278 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
279 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
280 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
281 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
284 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
285 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
286 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
287 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
288 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
289 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
294 #define CONFIG_ETHPRIME "eTSEC1"
296 #define CONFIG_TSEC1 1
297 #define CONFIG_TSEC1_NAME "eTSEC1"
298 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
299 #define TSEC1_PHY_ADDR 1
300 #define TSEC1_PHYIDX 0
301 #define CONFIG_HAS_ETH0
303 #define CONFIG_TSEC2 1
304 #define CONFIG_TSEC2_NAME "eTSEC2"
305 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
306 #define TSEC2_PHY_ADDR 2
307 #define TSEC2_PHYIDX 0
308 #define CONFIG_HAS_ETH1
313 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
314 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
318 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
322 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
325 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
329 * BAT0 2G Cacheable, non-guarded
332 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
333 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
334 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
335 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
338 * BAT1 1G Cache-inhibited, guarded
339 * 0x8000_0000 1G PCI-Express 1 Memory
341 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
345 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
349 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
352 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
355 * BAT2 512M Cache-inhibited, guarded
356 * 0xc000_0000 512M PCI-Express 2 Memory
358 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
362 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
366 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
369 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
372 * BAT3 1M Cache-inhibited, guarded
373 * 0xe000_0000 1M CCSR
375 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
379 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
383 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
386 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
389 * BAT4 32M Cache-inhibited, guarded
390 * 0xe200_0000 16M PCI-Express 1 I/O
391 * 0xe300_0000 16M PCI-Express 2 I/0
393 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
397 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
401 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
404 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
407 * BAT5 128K Cacheable, non-guarded
408 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
410 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
413 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
417 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
418 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
421 * BAT6 256M Cache-inhibited, guarded
422 * 0xf000_0000 256M FLASH
424 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
428 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
432 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
435 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
437 /* Map the last 1M of flash where we're running from reset */
438 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
442 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
446 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
449 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
452 * BAT7 64M Cache-inhibited, guarded
453 * 0xe800_0000 64K NAND FLASH
454 * 0xe804_0000 128K DUART Registers
456 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
460 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
464 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
467 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
470 * Miscellaneous configurable options
472 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
473 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
474 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
477 * For booting Linux, the board info and command line data
478 * have to be in the first 16 MB of memory, since this is
479 * the maximum mapped by the Linux kernel during initialization.
481 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
482 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
485 * Environment Configuration
490 * fffc0000 - ffffffff Pri FDT (256KB)
491 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
492 * fff00000 - fff7ffff Pri U-Boot (512 KB)
493 * fef00000 - ffefffff Pri OS image (16MB)
494 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
496 * f7fc0000 - f7ffffff Sec FDT (256KB)
497 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
498 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
499 * f6f00000 - f7efffff Sec OS image (16MB)
500 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
502 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
503 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
504 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
505 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
506 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
507 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
509 #define CONFIG_PROG_UBOOT1 \
510 "$download_cmd $loadaddr $ubootfile; " \
511 "if test $? -eq 0; then " \
512 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
513 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
514 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
515 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
516 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
517 "if test $? -ne 0; then " \
518 "echo PROGRAM FAILED; " \
520 "echo PROGRAM SUCCEEDED; " \
523 "echo DOWNLOAD FAILED; " \
526 #define CONFIG_PROG_UBOOT2 \
527 "$download_cmd $loadaddr $ubootfile; " \
528 "if test $? -eq 0; then " \
529 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
530 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
531 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
532 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
533 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
534 "if test $? -ne 0; then " \
535 "echo PROGRAM FAILED; " \
537 "echo PROGRAM SUCCEEDED; " \
540 "echo DOWNLOAD FAILED; " \
543 #define CONFIG_BOOT_OS_NET \
544 "$download_cmd $osaddr $osfile; " \
545 "if test $? -eq 0; then " \
546 "if test -n $fdtaddr; then " \
547 "$download_cmd $fdtaddr $fdtfile; " \
548 "if test $? -eq 0; then " \
549 "bootm $osaddr - $fdtaddr; " \
551 "echo FDT DOWNLOAD FAILED; " \
557 "echo OS DOWNLOAD FAILED; " \
560 #define CONFIG_PROG_OS1 \
561 "$download_cmd $osaddr $osfile; " \
562 "if test $? -eq 0; then " \
563 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
564 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
565 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
566 "if test $? -ne 0; then " \
567 "echo OS PROGRAM FAILED; " \
569 "echo OS PROGRAM SUCCEEDED; " \
572 "echo OS DOWNLOAD FAILED; " \
575 #define CONFIG_PROG_OS2 \
576 "$download_cmd $osaddr $osfile; " \
577 "if test $? -eq 0; then " \
578 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
579 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
580 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
581 "if test $? -ne 0; then " \
582 "echo OS PROGRAM FAILED; " \
584 "echo OS PROGRAM SUCCEEDED; " \
587 "echo OS DOWNLOAD FAILED; " \
590 #define CONFIG_PROG_FDT1 \
591 "$download_cmd $fdtaddr $fdtfile; " \
592 "if test $? -eq 0; then " \
593 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
594 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
595 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
596 "if test $? -ne 0; then " \
597 "echo FDT PROGRAM FAILED; " \
599 "echo FDT PROGRAM SUCCEEDED; " \
602 "echo FDT DOWNLOAD FAILED; " \
605 #define CONFIG_PROG_FDT2 \
606 "$download_cmd $fdtaddr $fdtfile; " \
607 "if test $? -eq 0; then " \
608 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
609 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
610 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
611 "if test $? -ne 0; then " \
612 "echo FDT PROGRAM FAILED; " \
614 "echo FDT PROGRAM SUCCEEDED; " \
617 "echo FDT DOWNLOAD FAILED; " \
620 #define CONFIG_EXTRA_ENV_SETTINGS \
622 "download_cmd=tftp\0" \
623 "console_args=console=ttyS0,115200\0" \
624 "root_args=root=/dev/nfs rw\0" \
625 "misc_args=ip=on\0" \
626 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
627 "bootfile=/home/user/file\0" \
628 "osfile=/home/user/board.uImage\0" \
629 "fdtfile=/home/user/board.dtb\0" \
630 "ubootfile=/home/user/u-boot.bin\0" \
631 "fdtaddr=0x1e00000\0" \
632 "osaddr=0x1000000\0" \
633 "loadaddr=0x1000000\0" \
634 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
635 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
636 "prog_os1="CONFIG_PROG_OS1"\0" \
637 "prog_os2="CONFIG_PROG_OS2"\0" \
638 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
639 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
640 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
641 "bootcmd_flash1=run set_bootargs; " \
642 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
643 "bootcmd_flash2=run set_bootargs; " \
644 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
645 "bootcmd=run bootcmd_flash1\0"
646 #endif /* __CONFIG_H */