1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration for Xilinx ZynqMP zcu106
5 * (C) Copyright 2016 Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
9 #ifndef __CONFIG_ZYNQMP_ZCU106_H
10 #define __CONFIG_ZYNQMP_ZCU106_H
12 #define CONFIG_ZYNQ_SDHCI1
13 #define CONFIG_SYS_I2C_MAX_HOPS 1
14 #define CONFIG_SYS_NUM_I2C_BUSES 18
15 #define CONFIG_SYS_I2C_BUSES { \
16 {0, {I2C_NULL_HOP} }, \
17 {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
18 {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
19 {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
20 {1, {I2C_NULL_HOP} }, \
21 {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
22 {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
23 {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
24 {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
25 {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
26 {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
27 {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
28 {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
29 {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
30 {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
31 {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
32 {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
33 {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
36 #define CONFIG_PCA953X
38 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
39 #define CONFIG_ZYNQ_EEPROM_BUS 5
40 #define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
42 #include <configs/xilinx_zynqmp.h>
44 #endif /* __CONFIG_ZYNQMP_ZCU106_H */