2 * Configuration for Xilinx ZynqMP emulation platforms
4 * (C) Copyright 2014 - 2015 Xilinx, Inc.
5 * Michal Simek <michal.simek@xilinx.com>
6 * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
8 * Based on Configuration for Versatile Express
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __CONFIG_ZYNQMP_EP_H
14 #define __CONFIG_ZYNQMP_EP_H
16 #define CONFIG_ZYNQ_SDHCI0
17 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000
18 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
19 #define CONFIG_ZYNQ_I2C0
20 #define CONFIG_SYS_I2C_ZYNQ
21 #define CONFIG_ZYNQ_EEPROM
23 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
24 ZYNQMP_USB1_XHCI_BASEADDR}
26 /* Physical Memory Map */
27 #define CONFIG_NR_DRAM_BANKS 1
28 #define CONFIG_SYS_SDRAM_BASE 0
29 #define CONFIG_SYS_SDRAM_SIZE 0x40000000
31 #define COUNTER_FREQUENCY 4000000
33 #include <configs/xilinx_zynqmp.h>
35 #endif /* __CONFIG_ZYNQMP_EP_H */