2 * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
3 * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
5 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
7 * SPDX-License-Identifier: GPL-2.0+
14 * High Level Configuration Options
17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */
18 #define CONFIG_X600 /* on X600 board */
20 #include <asm/arch/hardware.h>
22 /* Timer, HZ specific defines */
23 #define CONFIG_SYS_HZ_CLOCK 8300000
25 #define CONFIG_SYS_FLASH_BASE 0xf8000000
26 /* Reserve 8KiB for SPL */
27 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
28 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
29 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
31 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
32 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
33 #define CONFIG_SYS_MONITOR_LEN 0x60000
35 /* Serial Configuration (PL011) */
36 #define CONFIG_SYS_SERIAL0 0xD0000000
37 #define CONFIG_SYS_SERIAL1 0xD0080000
38 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
39 (void *)CONFIG_SYS_SERIAL1 }
40 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
41 #define CONFIG_CONS_INDEX 0
42 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
44 #define CONFIG_SYS_LOADS_BAUD_CHANGE
46 /* NOR FLASH config options */
48 #define CONFIG_SYS_MAX_FLASH_BANKS 1
49 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
50 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
51 #define CONFIG_SYS_MAX_FLASH_SECT 128
52 #define CONFIG_SYS_FLASH_EMPTY_INFO
53 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
54 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
56 /* NAND FLASH config options */
57 #define CONFIG_NAND_FSMC
58 #define CONFIG_SYS_NAND_SELF_INIT
59 #define CONFIG_SYS_MAX_NAND_DEVICE 1
60 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
61 #define CONFIG_MTD_ECC_SOFT
62 #define CONFIG_SYS_FSMC_NAND_8BIT
63 #define CONFIG_SYS_NAND_ONFI_DETECTION
64 #define CONFIG_NAND_ECC_BCH
66 /* UBI/UBI config options */
67 #define CONFIG_MTD_DEVICE
68 #define CONFIG_MTD_PARTITIONS
70 /* Ethernet config options */
72 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
73 #define CONFIG_PHY_ADDR 0 /* PHY address */
75 #define CONFIG_SPEAR_GPIO
77 /* I2C config options */
78 #define CONFIG_SYS_I2C
79 #define CONFIG_SYS_I2C_BASE 0xD0200000
80 #define CONFIG_SYS_I2C_SPEED 400000
81 #define CONFIG_SYS_I2C_SLAVE 0x02
82 #define CONFIG_I2C_CHIPADDRESS 0x50
84 #define CONFIG_RTC_M41T62 1
85 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
87 /* FPGA config options */
88 #define CONFIG_FPGA_COUNT 1
90 /* USB EHCI options */
91 #define CONFIG_USB_EHCI_SPEAR
92 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
95 * U-Boot Environment placing definitions.
97 #define CONFIG_ENV_SECT_SIZE 0x00010000
98 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
99 CONFIG_SYS_MONITOR_LEN)
100 #define CONFIG_ENV_SIZE 0x02000
101 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
102 CONFIG_ENV_SECT_SIZE)
103 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
105 /* Miscellaneous configurable options */
106 #define CONFIG_ARCH_CPU_INIT
107 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100
108 #define CONFIG_CMDLINE_TAG
109 #define CONFIG_SETUP_MEMORY_TAGS
110 #define CONFIG_MISC_INIT_R
111 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
113 #define CONFIG_SYS_MEMTEST_START 0x00800000
114 #define CONFIG_SYS_MEMTEST_END 0x04000000
115 #define CONFIG_SYS_MALLOC_LEN (8 << 20)
116 #define CONFIG_SYS_LOAD_ADDR 0x00800000
118 #define CONFIG_HOSTNAME x600
119 #define CONFIG_UBI_PART ubi0
120 #define CONFIG_UBIFS_VOLUME rootfs
122 #define CONFIG_EXTRA_ENV_SETTINGS \
123 "u-boot_addr=1000000\0" \
124 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
125 "load=tftp ${u-boot_addr} ${u-boot}\0" \
126 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
128 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
129 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
131 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
133 "upd=run load update\0" \
134 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
135 "part=" __stringify(CONFIG_UBI_PART) "\0" \
136 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
137 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
138 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
140 "upd_ubifs=run load_ubifs update_ubifs\0" \
141 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
142 "ubi create ${vol} 4000000\0" \
144 "rootpath=/opt/eldk-4.2/arm\0" \
145 "nfsargs=setenv bootargs root=/dev/nfs rw " \
146 "nfsroot=${serverip}:${rootpath}\0" \
147 "ramargs=setenv bootargs root=/dev/ram rw\0" \
149 "altbootcmd=if test $boot_part -eq 0;then " \
150 "echo Switching to partition 1!;" \
151 "setenv boot_part 1;" \
153 "echo Switching to partition 0!;" \
154 "setenv boot_part 0;" \
157 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
158 "root=ubi0:rootfs rootfstype=ubifs\0" \
159 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
160 "kernel_fs=/boot/uImage \0" \
161 "kernel_addr=1000000\0" \
162 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
163 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
164 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
165 "dtb_addr=1800000\0" \
166 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
167 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
168 "addip=setenv bootargs ${bootargs} " \
169 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
170 ":${hostname}:${netdev}:off panic=1\0" \
171 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
173 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
174 "net_nfs=run load_dtb load_kernel; " \
175 "run nfsargs addip addcon addmtd addmisc;" \
176 "bootm ${kernel_addr} - ${dtb_addr}\0" \
177 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
178 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
179 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
180 " addcon addmisc addmtd;" \
181 "bootm ${kernel_addr} - ${dtb_addr}\0" \
182 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
183 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
184 "ubifsload ${dtb_addr} ${dtb_fs};\0" \
185 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
186 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
187 "bootcmd=run nand_ubifs\0" \
190 /* Physical Memory Map */
191 #define CONFIG_NR_DRAM_BANKS 1
192 #define PHYS_SDRAM_1 0x00000000
193 #define PHYS_SDRAM_1_MAXSIZE 0x40000000
195 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
196 #define CONFIG_SRAM_BASE 0xd2800000
197 /* Preserve the last 2 lwords for the boot-counter */
198 #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
199 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
200 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
202 #define CONFIG_SYS_INIT_SP_OFFSET \
203 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
205 #define CONFIG_SYS_INIT_SP_ADDR \
206 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
209 * SPL related defines
211 #define CONFIG_SPL_TEXT_BASE 0xd2800b00
212 #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
213 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
216 * Please select/define only one of the following
217 * Each definition corresponds to a supported DDR chip.
218 * DDR configuration is based on the following selection
220 #define CONFIG_DDR_MT47H64M16 1
221 #define CONFIG_DDR_MT47H32M16 0
222 #define CONFIG_DDR_MT47H128M8 0
225 * Synchronous/Asynchronous operation of DDR
227 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
228 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
229 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
231 #define CONFIG_DDR_2HCLK 1
232 #define CONFIG_DDR_HCLK 0
233 #define CONFIG_DDR_PLL2 0
236 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
237 * or not. Modify/Add to only these macros to define new boot types
239 #define USB_BOOT_SUPPORTED 0
240 #define PCIE_BOOT_SUPPORTED 0
241 #define SNOR_BOOT_SUPPORTED 1
242 #define NAND_BOOT_SUPPORTED 1
243 #define PNOR_BOOT_SUPPORTED 0
244 #define TFTP_BOOT_SUPPORTED 0
245 #define UART_BOOT_SUPPORTED 0
246 #define SPI_BOOT_SUPPORTED 0
247 #define I2C_BOOT_SUPPORTED 0
248 #define MMC_BOOT_SUPPORTED 0
250 #endif /* __CONFIG_H */