3 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
5 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
7 * SPDX-License-Identifier: GPL-2.0+
14 * High Level Configuration Options
17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */
18 #define CONFIG_X600 /* on X600 board */
20 #include <asm/arch/hardware.h>
22 /* Timer, HZ specific defines */
23 #define CONFIG_SYS_HZ_CLOCK 8300000
25 #define CONFIG_SYS_TEXT_BASE 0x00800040
26 #define CONFIG_SYS_FLASH_BASE 0xf8000000
27 /* Reserve 8KiB for SPL */
28 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
29 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
30 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
32 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
34 #define CONFIG_SYS_MONITOR_LEN 0x60000
36 /* Serial Configuration (PL011) */
37 #define CONFIG_SYS_SERIAL0 0xD0000000
38 #define CONFIG_SYS_SERIAL1 0xD0080000
39 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
40 (void *)CONFIG_SYS_SERIAL1 }
41 #define CONFIG_PL011_SERIAL
42 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
43 #define CONFIG_CONS_INDEX 0
44 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
46 #define CONFIG_SYS_LOADS_BAUD_CHANGE
48 /* NOR FLASH config options */
50 #define CONFIG_SYS_MAX_FLASH_BANKS 1
51 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
52 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
53 #define CONFIG_SYS_MAX_FLASH_SECT 128
54 #define CONFIG_SYS_FLASH_EMPTY_INFO
55 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
56 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
58 /* NAND FLASH config options */
59 #define CONFIG_NAND_FSMC
60 #define CONFIG_SYS_NAND_SELF_INIT
61 #define CONFIG_SYS_MAX_NAND_DEVICE 1
62 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
63 #define CONFIG_MTD_ECC_SOFT
64 #define CONFIG_SYS_FSMC_NAND_8BIT
65 #define CONFIG_SYS_NAND_ONFI_DETECTION
66 #define CONFIG_NAND_ECC_BCH
69 /* UBI/UBI config options */
70 #define CONFIG_MTD_DEVICE
71 #define CONFIG_MTD_PARTITIONS
73 /* Ethernet config options */
75 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
76 #define CONFIG_PHY_ADDR 0 /* PHY address */
77 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
79 #define CONFIG_SPEAR_GPIO
81 /* I2C config options */
82 #define CONFIG_SYS_I2C
83 #define CONFIG_SYS_I2C_BASE 0xD0200000
84 #define CONFIG_SYS_I2C_SPEED 400000
85 #define CONFIG_SYS_I2C_SLAVE 0x02
86 #define CONFIG_I2C_CHIPADDRESS 0x50
88 #define CONFIG_RTC_M41T62 1
89 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
91 /* FPGA config options */
93 #define CONFIG_FPGA_XILINX
94 #define CONFIG_FPGA_SPARTAN3
95 #define CONFIG_FPGA_COUNT 1
97 /* USB EHCI options */
98 #define CONFIG_USB_EHCI_SPEAR
99 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
102 * Command support defines
104 #define CONFIG_CMD_SAVES
106 /* Filesystem support (for USB key) */
107 #define CONFIG_SUPPORT_VFAT
111 * U-Boot Environment placing definitions.
113 #define CONFIG_ENV_SECT_SIZE 0x00010000
114 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
115 CONFIG_SYS_MONITOR_LEN)
116 #define CONFIG_ENV_SIZE 0x02000
117 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
118 CONFIG_ENV_SECT_SIZE)
119 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
121 /* Miscellaneous configurable options */
122 #define CONFIG_ARCH_CPU_INIT
123 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100
124 #define CONFIG_CMDLINE_TAG
125 #define CONFIG_SETUP_MEMORY_TAGS
126 #define CONFIG_MISC_INIT_R
127 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
129 #define CONFIG_SYS_MEMTEST_START 0x00800000
130 #define CONFIG_SYS_MEMTEST_END 0x04000000
131 #define CONFIG_SYS_MALLOC_LEN (8 << 20)
132 #define CONFIG_SYS_LONGHELP
133 #define CONFIG_CMDLINE_EDITING
134 #define CONFIG_AUTO_COMPLETE
135 #define CONFIG_SYS_CBSIZE 256
136 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
137 sizeof(CONFIG_SYS_PROMPT) + 16)
138 #define CONFIG_SYS_MAXARGS 16
139 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
140 #define CONFIG_SYS_LOAD_ADDR 0x00800000
142 /* Use last 2 lwords in internal SRAM for bootcounter */
143 #define CONFIG_BOOTCOUNT_LIMIT
144 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \
147 #define CONFIG_HOSTNAME x600
148 #define CONFIG_UBI_PART ubi0
149 #define CONFIG_UBIFS_VOLUME rootfs
151 #define MTDIDS_DEFAULT "nand0=nand"
152 #define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)"
154 #define CONFIG_EXTRA_ENV_SETTINGS \
155 "u-boot_addr=1000000\0" \
156 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
157 "load=tftp ${u-boot_addr} ${u-boot}\0" \
158 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
160 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
161 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
163 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
165 "upd=run load update\0" \
166 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
167 "part=" __stringify(CONFIG_UBI_PART) "\0" \
168 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
169 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
170 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
172 "upd_ubifs=run load_ubifs update_ubifs\0" \
173 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
174 "ubi create ${vol} 4000000\0" \
176 "rootpath=/opt/eldk-4.2/arm\0" \
177 "nfsargs=setenv bootargs root=/dev/nfs rw " \
178 "nfsroot=${serverip}:${rootpath}\0" \
179 "ramargs=setenv bootargs root=/dev/ram rw\0" \
181 "altbootcmd=if test $boot_part -eq 0;then " \
182 "echo Switching to partition 1!;" \
183 "setenv boot_part 1;" \
185 "echo Switching to partition 0!;" \
186 "setenv boot_part 0;" \
189 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
190 "root=ubi0:rootfs rootfstype=ubifs\0" \
191 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
192 "kernel_fs=/boot/uImage \0" \
193 "kernel_addr=1000000\0" \
194 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
195 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
196 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
197 "dtb_addr=1800000\0" \
198 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
199 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
200 "addip=setenv bootargs ${bootargs} " \
201 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
202 ":${hostname}:${netdev}:off panic=1\0" \
203 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
205 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
206 "net_nfs=run load_dtb load_kernel; " \
207 "run nfsargs addip addcon addmtd addmisc;" \
208 "bootm ${kernel_addr} - ${dtb_addr}\0" \
209 "mtdids=" MTDIDS_DEFAULT "\0" \
210 "mtdparts=" MTDPARTS_DEFAULT "\0" \
211 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
212 " addcon addmisc addmtd;" \
213 "bootm ${kernel_addr} - ${dtb_addr}\0" \
214 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
215 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
216 "ubifsload ${dtb_addr} ${dtb_fs};\0" \
217 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
218 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
219 "bootcmd=run nand_ubifs\0" \
222 /* Physical Memory Map */
223 #define CONFIG_NR_DRAM_BANKS 1
224 #define PHYS_SDRAM_1 0x00000000
225 #define PHYS_SDRAM_1_MAXSIZE 0x40000000
227 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
228 #define CONFIG_SRAM_BASE 0xd2800000
229 /* Preserve the last 2 lwords for the boot-counter */
230 #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
231 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
232 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
234 #define CONFIG_SYS_INIT_SP_OFFSET \
235 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
237 #define CONFIG_SYS_INIT_SP_ADDR \
238 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
241 * SPL related defines
243 #define CONFIG_SPL_TEXT_BASE 0xd2800b00
244 #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
245 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
246 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds"
248 #define CONFIG_SPL_FRAMEWORK
251 * Please select/define only one of the following
252 * Each definition corresponds to a supported DDR chip.
253 * DDR configuration is based on the following selection
255 #define CONFIG_DDR_MT47H64M16 1
256 #define CONFIG_DDR_MT47H32M16 0
257 #define CONFIG_DDR_MT47H128M8 0
260 * Synchronous/Asynchronous operation of DDR
262 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
263 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
264 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
266 #define CONFIG_DDR_2HCLK 1
267 #define CONFIG_DDR_HCLK 0
268 #define CONFIG_DDR_PLL2 0
271 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
272 * or not. Modify/Add to only these macros to define new boot types
274 #define USB_BOOT_SUPPORTED 0
275 #define PCIE_BOOT_SUPPORTED 0
276 #define SNOR_BOOT_SUPPORTED 1
277 #define NAND_BOOT_SUPPORTED 1
278 #define PNOR_BOOT_SUPPORTED 0
279 #define TFTP_BOOT_SUPPORTED 0
280 #define UART_BOOT_SUPPORTED 0
281 #define SPI_BOOT_SUPPORTED 0
282 #define I2C_BOOT_SUPPORTED 0
283 #define MMC_BOOT_SUPPORTED 0
285 #endif /* __CONFIG_H */