2 * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
3 * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
5 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
7 * SPDX-License-Identifier: GPL-2.0+
14 * High Level Configuration Options
17 #define CONFIG_SPEAR600 /* SPEAr600 SoC */
18 #define CONFIG_X600 /* on X600 board */
20 #include <asm/arch/hardware.h>
22 /* Timer, HZ specific defines */
23 #define CONFIG_SYS_HZ_CLOCK 8300000
25 #define CONFIG_SYS_TEXT_BASE 0x00800040
26 #define CONFIG_SYS_FLASH_BASE 0xf8000000
27 /* Reserve 8KiB for SPL */
28 #define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
29 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
30 #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
32 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
34 #define CONFIG_SYS_MONITOR_LEN 0x60000
36 /* Serial Configuration (PL011) */
37 #define CONFIG_SYS_SERIAL0 0xD0000000
38 #define CONFIG_SYS_SERIAL1 0xD0080000
39 #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
40 (void *)CONFIG_SYS_SERIAL1 }
41 #define CONFIG_PL011_SERIAL
42 #define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
43 #define CONFIG_CONS_INDEX 0
44 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
46 #define CONFIG_SYS_LOADS_BAUD_CHANGE
48 /* NOR FLASH config options */
50 #define CONFIG_SYS_MAX_FLASH_BANKS 1
51 #define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
52 #define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
53 #define CONFIG_SYS_MAX_FLASH_SECT 128
54 #define CONFIG_SYS_FLASH_EMPTY_INFO
55 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
56 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
58 /* NAND FLASH config options */
59 #define CONFIG_NAND_FSMC
60 #define CONFIG_SYS_NAND_SELF_INIT
61 #define CONFIG_SYS_MAX_NAND_DEVICE 1
62 #define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
63 #define CONFIG_MTD_ECC_SOFT
64 #define CONFIG_SYS_FSMC_NAND_8BIT
65 #define CONFIG_SYS_NAND_ONFI_DETECTION
66 #define CONFIG_NAND_ECC_BCH
68 /* UBI/UBI config options */
69 #define CONFIG_MTD_DEVICE
70 #define CONFIG_MTD_PARTITIONS
72 /* Ethernet config options */
74 #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
75 #define CONFIG_PHY_ADDR 0 /* PHY address */
77 #define CONFIG_SPEAR_GPIO
79 /* I2C config options */
80 #define CONFIG_SYS_I2C
81 #define CONFIG_SYS_I2C_BASE 0xD0200000
82 #define CONFIG_SYS_I2C_SPEED 400000
83 #define CONFIG_SYS_I2C_SLAVE 0x02
84 #define CONFIG_I2C_CHIPADDRESS 0x50
86 #define CONFIG_RTC_M41T62 1
87 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
89 /* FPGA config options */
91 #define CONFIG_FPGA_XILINX
92 #define CONFIG_FPGA_SPARTAN3
93 #define CONFIG_FPGA_COUNT 1
95 /* USB EHCI options */
96 #define CONFIG_USB_EHCI_SPEAR
97 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
100 * U-Boot Environment placing definitions.
102 #define CONFIG_ENV_SECT_SIZE 0x00010000
103 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
104 CONFIG_SYS_MONITOR_LEN)
105 #define CONFIG_ENV_SIZE 0x02000
106 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
107 CONFIG_ENV_SECT_SIZE)
108 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
110 /* Miscellaneous configurable options */
111 #define CONFIG_ARCH_CPU_INIT
112 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100
113 #define CONFIG_CMDLINE_TAG
114 #define CONFIG_SETUP_MEMORY_TAGS
115 #define CONFIG_MISC_INIT_R
116 #define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
118 #define CONFIG_SYS_MEMTEST_START 0x00800000
119 #define CONFIG_SYS_MEMTEST_END 0x04000000
120 #define CONFIG_SYS_MALLOC_LEN (8 << 20)
121 #define CONFIG_SYS_LONGHELP
122 #define CONFIG_CMDLINE_EDITING
123 #define CONFIG_AUTO_COMPLETE
124 #define CONFIG_SYS_LOAD_ADDR 0x00800000
126 /* Use last 2 lwords in internal SRAM for bootcounter */
127 #define CONFIG_BOOTCOUNT_LIMIT
128 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \
131 #define CONFIG_HOSTNAME x600
132 #define CONFIG_UBI_PART ubi0
133 #define CONFIG_UBIFS_VOLUME rootfs
135 #define CONFIG_EXTRA_ENV_SETTINGS \
136 "u-boot_addr=1000000\0" \
137 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
138 "load=tftp ${u-boot_addr} ${u-boot}\0" \
139 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
141 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
142 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
144 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
146 "upd=run load update\0" \
147 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
148 "part=" __stringify(CONFIG_UBI_PART) "\0" \
149 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
150 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
151 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
153 "upd_ubifs=run load_ubifs update_ubifs\0" \
154 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
155 "ubi create ${vol} 4000000\0" \
157 "rootpath=/opt/eldk-4.2/arm\0" \
158 "nfsargs=setenv bootargs root=/dev/nfs rw " \
159 "nfsroot=${serverip}:${rootpath}\0" \
160 "ramargs=setenv bootargs root=/dev/ram rw\0" \
162 "altbootcmd=if test $boot_part -eq 0;then " \
163 "echo Switching to partition 1!;" \
164 "setenv boot_part 1;" \
166 "echo Switching to partition 0!;" \
167 "setenv boot_part 0;" \
170 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
171 "root=ubi0:rootfs rootfstype=ubifs\0" \
172 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
173 "kernel_fs=/boot/uImage \0" \
174 "kernel_addr=1000000\0" \
175 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
176 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
177 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
178 "dtb_addr=1800000\0" \
179 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
180 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
181 "addip=setenv bootargs ${bootargs} " \
182 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
183 ":${hostname}:${netdev}:off panic=1\0" \
184 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
186 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
187 "net_nfs=run load_dtb load_kernel; " \
188 "run nfsargs addip addcon addmtd addmisc;" \
189 "bootm ${kernel_addr} - ${dtb_addr}\0" \
190 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
191 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
192 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
193 " addcon addmisc addmtd;" \
194 "bootm ${kernel_addr} - ${dtb_addr}\0" \
195 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
196 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
197 "ubifsload ${dtb_addr} ${dtb_fs};\0" \
198 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
199 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
200 "bootcmd=run nand_ubifs\0" \
203 /* Physical Memory Map */
204 #define CONFIG_NR_DRAM_BANKS 1
205 #define PHYS_SDRAM_1 0x00000000
206 #define PHYS_SDRAM_1_MAXSIZE 0x40000000
208 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
209 #define CONFIG_SRAM_BASE 0xd2800000
210 /* Preserve the last 2 lwords for the boot-counter */
211 #define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
212 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
213 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
215 #define CONFIG_SYS_INIT_SP_OFFSET \
216 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
218 #define CONFIG_SYS_INIT_SP_ADDR \
219 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
222 * SPL related defines
224 #define CONFIG_SPL_TEXT_BASE 0xd2800b00
225 #define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
226 #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
228 #define CONFIG_SPL_FRAMEWORK
231 * Please select/define only one of the following
232 * Each definition corresponds to a supported DDR chip.
233 * DDR configuration is based on the following selection
235 #define CONFIG_DDR_MT47H64M16 1
236 #define CONFIG_DDR_MT47H32M16 0
237 #define CONFIG_DDR_MT47H128M8 0
240 * Synchronous/Asynchronous operation of DDR
242 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
243 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
244 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
246 #define CONFIG_DDR_2HCLK 1
247 #define CONFIG_DDR_HCLK 0
248 #define CONFIG_DDR_PLL2 0
251 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
252 * or not. Modify/Add to only these macros to define new boot types
254 #define USB_BOOT_SUPPORTED 0
255 #define PCIE_BOOT_SUPPORTED 0
256 #define SNOR_BOOT_SUPPORTED 1
257 #define NAND_BOOT_SUPPORTED 1
258 #define PNOR_BOOT_SUPPORTED 0
259 #define TFTP_BOOT_SUPPORTED 0
260 #define UART_BOOT_SUPPORTED 0
261 #define SPI_BOOT_SUPPORTED 0
262 #define I2C_BOOT_SUPPORTED 0
263 #define MMC_BOOT_SUPPORTED 0
265 #endif /* __CONFIG_H */