1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * WORK Microwave work_92105 board configuration file
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
9 #ifndef __CONFIG_WORK_92105_H__
10 #define __CONFIG_WORK_92105_H__
12 /* SoC and board defines */
13 #include <linux/sizes.h>
14 #include <asm/arch/cpu.h>
17 * Memory configurations
19 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
20 #define CONFIG_SYS_SDRAM_SIZE SZ_128M
22 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
23 - GENERATED_GBL_DATA_SIZE)
25 #define CONFIG_RTC_DS1374
28 * U-Boot General Configurations
30 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
33 * NAND chip timings for FIXME: which one?
36 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
37 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
38 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
39 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
40 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
41 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
42 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
48 /* driver configuration */
49 #define CONFIG_SYS_MAX_NAND_DEVICE 1
50 #define CONFIG_SYS_MAX_NAND_CHIPS 1
51 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
65 /* SPL will be executed at offset 0 */
66 /* SPL will use SRAM as stack */
67 #define CONFIG_SPL_STACK 0x0000FFF8
68 /* Use the framework and generic lib */
69 /* SPL will use serial */
70 /* SPL will load U-Boot from NAND offset 0x40000 */
71 #define CONFIG_SPL_PAD_TO 0x20000
72 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
73 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
74 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
75 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
78 * Include SoC specific configuration
80 #include <asm/arch/config.h>
82 #endif /* __CONFIG_WORK_92105_H__*/