1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * WORK Microwave work_92105 board configuration file
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
9 #ifndef __CONFIG_WORK_92105_H__
10 #define __CONFIG_WORK_92105_H__
12 /* SoC and board defines */
13 #include <linux/sizes.h>
14 #include <asm/arch/cpu.h>
17 * Memory configurations
19 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
20 #define CONFIG_SYS_SDRAM_SIZE SZ_128M
22 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
23 - GENERATED_GBL_DATA_SIZE)
25 #define CONFIG_RTC_DS1374
28 * U-Boot General Configurations
32 * NAND chip timings for FIXME: which one?
35 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
36 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
37 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
38 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
39 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
40 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
41 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
47 /* driver configuration */
48 #define CONFIG_SYS_MAX_NAND_DEVICE 1
49 #define CONFIG_SYS_MAX_NAND_CHIPS 1
50 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
64 /* SPL will be executed at offset 0 */
65 /* SPL will use SRAM as stack */
66 #define CONFIG_SPL_STACK 0x0000FFF8
67 /* Use the framework and generic lib */
68 /* SPL will use serial */
69 /* SPL will load U-Boot from NAND offset 0x40000 */
70 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
71 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
72 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
73 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
76 * Include SoC specific configuration
78 #include <asm/arch/config.h>
80 #endif /* __CONFIG_WORK_92105_H__*/