1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * WORK Microwave work_92105 board configuration file
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
9 #ifndef __CONFIG_WORK_92105_H__
10 #define __CONFIG_WORK_92105_H__
12 /* SoC and board defines */
13 #include <linux/sizes.h>
14 #include <asm/arch/cpu.h>
17 * Define work_92105 machine type by hand -- done only for compatibility
18 * with original board code
20 #define CONFIG_MACH_TYPE 736
22 #if !defined(CONFIG_SPL_BUILD)
23 #define CONFIG_SKIP_LOWLEVEL_INIT
27 * Memory configurations
29 #define CONFIG_SYS_MALLOC_LEN SZ_1M
30 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
31 #define CONFIG_SYS_SDRAM_SIZE SZ_128M
32 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
33 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
35 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
37 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
38 - GENERATED_GBL_DATA_SIZE)
43 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
49 #define CONFIG_PHY_SMSC
50 #define CONFIG_LPC32XX_ETH
51 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
52 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
58 #define CONFIG_SYS_I2C_LPC32XX
59 #define CONFIG_SYS_I2C
60 #define CONFIG_SYS_I2C_SPEED 350000
66 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
67 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
73 #define CONFIG_RTC_DS1374
76 * U-Boot General Configurations
78 #define CONFIG_SYS_CBSIZE 1024
79 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
82 * NAND chip timings for FIXME: which one?
85 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
86 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
87 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
88 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
89 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
90 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
91 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
97 /* driver configuration */
98 #define CONFIG_SYS_NAND_SELF_INIT
99 #define CONFIG_SYS_MAX_NAND_DEVICE 1
100 #define CONFIG_SYS_MAX_NAND_CHIPS 1
101 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
102 #define CONFIG_NAND_LPC32XX_MLC
108 #define CONFIG_LPC32XX_GPIO
114 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
119 #define CONFIG_ENV_SIZE 0x00020000
120 #define CONFIG_ENV_OFFSET 0x00100000
121 #define CONFIG_ENV_OFFSET_REDUND 0x00120000
122 #define CONFIG_ENV_ADDR 0x80000100
127 #define CONFIG_CMDLINE_TAG
128 #define CONFIG_SETUP_MEMORY_TAGS
129 #define CONFIG_INITRD_TAG
131 #define CONFIG_BOOTFILE "uImage"
132 #define CONFIG_LOADADDR 0x80008000
138 /* SPL will be executed at offset 0 */
139 /* SPL will use SRAM as stack */
140 #define CONFIG_SPL_STACK 0x0000FFF8
141 /* Use the framework and generic lib */
142 /* SPL will use serial */
143 /* SPL will load U-Boot from NAND offset 0x40000 */
144 #define CONFIG_SPL_NAND_DRIVERS
145 #define CONFIG_SPL_NAND_BASE
146 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
147 #define CONFIG_SPL_PAD_TO 0x20000
148 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
149 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
150 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
151 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
154 * Include SoC specific configuration
156 #include <asm/arch/config.h>
158 #endif /* __CONFIG_WORK_92105_H__*/