2 * Copyright (C) 2016 NXP Semiconductors
4 * Configuration settings for the i.MX7S Warp board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __WARP7_CONFIG_H
10 #define __WARP7_CONFIG_H
12 #include "mx7_common.h"
14 #define PHYS_SDRAM_SIZE SZ_512M
16 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
18 /* Size of malloc() pool */
19 #define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
22 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
23 #define CONFIG_SUPPORT_EMMC_BOOT
24 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
25 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
27 /* Switch on SERIAL_TAG */
28 #define CONFIG_SERIAL_TAG
30 #define CONFIG_DFU_ENV_SETTINGS \
31 "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
33 #define CONFIG_EXTRA_ENV_SETTINGS \
34 CONFIG_DFU_ENV_SETTINGS \
38 "ethact=usb_ether\0" \
39 "fdt_high=0xffffffff\0" \
40 "initrd_high=0xffffffff\0" \
41 "fdt_file=imx7s-warp.dtb\0" \
42 "fdt_addr=0x83000000\0" \
45 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
46 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
47 "finduuid=part uuid mmc 0:2 uuid\0" \
48 "mmcargs=setenv bootargs console=${console},${baudrate} " \
49 "root=PARTUUID=${uuid} rootwait rw\0" \
51 "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
52 "bootscript=echo Running bootscript from mmc ...; " \
54 "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
55 "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
56 "mmcboot=echo Booting from mmc ...; " \
59 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
60 "if run loadfdt; then " \
61 "bootz ${loadaddr} - ${fdt_addr}; " \
63 "if test ${boot_fdt} = try; then " \
66 "echo WARN: Cannot load the DT; " \
73 #define CONFIG_BOOTCOMMAND \
74 "mmc dev ${mmcdev};" \
75 "mmc dev ${mmcdev}; if mmc rescan; then " \
76 "if run loadbootscript; then " \
79 "if run loadimage; then " \
85 #define CONFIG_SYS_MEMTEST_START 0x80000000
86 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
88 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
89 #define CONFIG_SYS_HZ 1000
91 /* Physical Memory Map */
92 #define CONFIG_NR_DRAM_BANKS 1
93 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
95 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
96 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
97 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
99 #define CONFIG_SYS_INIT_SP_OFFSET \
100 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
101 #define CONFIG_SYS_INIT_SP_ADDR \
102 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
105 #define CONFIG_SYS_I2C
106 #define CONFIG_SYS_I2C_MXC
107 #define CONFIG_SYS_I2C_MXC_I2C1
108 #define CONFIG_SYS_I2C_SPEED 100000
112 #define CONFIG_POWER_I2C
113 #define CONFIG_POWER_PFUZE3000
114 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
116 /* environment organization */
117 #define CONFIG_ENV_SIZE SZ_8K
119 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
120 #define CONFIG_SYS_FSL_USDHC_NUM 1
122 #define CONFIG_SYS_MMC_ENV_DEV 0
123 #define CONFIG_SYS_MMC_ENV_PART 0
126 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
128 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
129 #define CONFIG_MXC_USB_FLAGS 0
130 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
132 #define CONFIG_IMX_THERMAL
134 #define CONFIG_USBD_HS
136 /* USB Device Firmware Update support */
137 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
138 #define DFU_DEFAULT_POLL_TIMEOUT 300
140 #define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01"