2 * Copyright (C) 2016 NXP Semiconductors
4 * Configuration settings for the i.MX7S Warp board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __WARP7_CONFIG_H
10 #define __WARP7_CONFIG_H
12 #include "mx7_common.h"
14 #define PHYS_SDRAM_SIZE SZ_512M
16 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
18 /* Size of malloc() pool */
19 #define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
21 #define CONFIG_BOARD_EARLY_INIT_F
22 #define CONFIG_BOARD_LATE_INIT
24 #define CONFIG_DISPLAY_BOARDINFO
27 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
28 #define CONFIG_SUPPORT_EMMC_BOOT
29 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
30 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
32 #define CONFIG_PARTITION_UUIDS
33 #define CONFIG_CMD_PART
35 #define CONFIG_DFU_ENV_SETTINGS \
36 "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
38 #define CONFIG_EXTRA_ENV_SETTINGS \
39 CONFIG_DFU_ENV_SETTINGS \
43 "fdt_high=0xffffffff\0" \
44 "initrd_high=0xffffffff\0" \
45 "fdt_file=imx7s-warp.dtb\0" \
46 "fdt_addr=0x83000000\0" \
49 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
50 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
51 "finduuid=part uuid mmc 0:2 uuid\0" \
52 "mmcargs=setenv bootargs console=${console},${baudrate} " \
53 "root=PARTUUID=${uuid} rootwait rw\0" \
55 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
56 "bootscript=echo Running bootscript from mmc ...; " \
58 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
59 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
60 "mmcboot=echo Booting from mmc ...; " \
63 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
64 "if run loadfdt; then " \
65 "bootz ${loadaddr} - ${fdt_addr}; " \
67 "if test ${boot_fdt} = try; then " \
70 "echo WARN: Cannot load the DT; " \
77 #define CONFIG_BOOTCOMMAND \
78 "mmc dev ${mmcdev};" \
79 "mmc dev ${mmcdev}; if mmc rescan; then " \
80 "if run loadbootscript; then " \
83 "if run loadimage; then " \
89 #define CONFIG_SYS_MEMTEST_START 0x80000000
90 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
92 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
93 #define CONFIG_SYS_HZ 1000
95 #define CONFIG_STACKSIZE SZ_128K
97 /* Physical Memory Map */
98 #define CONFIG_NR_DRAM_BANKS 1
99 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
101 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
102 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
103 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
105 #define CONFIG_SYS_INIT_SP_OFFSET \
106 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
107 #define CONFIG_SYS_INIT_SP_ADDR \
108 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
111 #define CONFIG_SYS_I2C
112 #define CONFIG_SYS_I2C_MXC
113 #define CONFIG_SYS_I2C_MXC_I2C1
114 #define CONFIG_SYS_I2C_SPEED 100000
118 #define CONFIG_POWER_I2C
119 #define CONFIG_POWER_PFUZE3000
120 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
122 /* FLASH and environment organization */
123 #define CONFIG_SYS_NO_FLASH
124 #define CONFIG_ENV_SIZE SZ_8K
125 #define CONFIG_ENV_IS_IN_MMC
127 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
128 #define CONFIG_SYS_FSL_USDHC_NUM 1
130 #define CONFIG_SYS_MMC_ENV_DEV 0
131 #define CONFIG_SYS_MMC_ENV_PART 0
134 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
136 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
137 #define CONFIG_MXC_USB_FLAGS 0
138 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
140 #define CONFIG_IMX_THERMAL
142 #define CONFIG_USBD_HS
144 #define CONFIG_USB_FUNCTION_MASS_STORAGE
146 /* USB Device Firmware Update support */
147 #define CONFIG_USB_FUNCTION_DFU
148 #define CONFIG_DFU_MMC
149 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
150 #define DFU_DEFAULT_POLL_TIMEOUT 300