2 * Copyright (C) 2016 NXP Semiconductors
4 * Configuration settings for the i.MX7S Warp board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __WARP7_CONFIG_H
10 #define __WARP7_CONFIG_H
12 #include "mx7_common.h"
14 #define PHYS_SDRAM_SIZE SZ_512M
16 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
18 /* Size of malloc() pool */
19 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
21 #define CONFIG_BOARD_EARLY_INIT_F
22 #define CONFIG_BOARD_LATE_INIT
25 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
26 #define CONFIG_SUPPORT_EMMC_BOOT
27 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
28 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
30 #define CONFIG_DFU_ENV_SETTINGS \
31 "dfu_alt_info=image raw 0 0x800000;"\
32 "u-boot raw 0 0x4000;"\
36 #define CONFIG_EXTRA_ENV_SETTINGS \
37 CONFIG_DFU_ENV_SETTINGS \
41 "fdt_high=0xffffffff\0" \
42 "initrd_high=0xffffffff\0" \
43 "fdt_file=imx7d-warp.dtb\0" \
44 "fdt_addr=0x83000000\0" \
47 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
48 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
49 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
50 "mmcargs=setenv bootargs console=${console},${baudrate} " \
53 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
54 "bootscript=echo Running bootscript from mmc ...; " \
56 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
57 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
58 "mmcboot=echo Booting from mmc ...; " \
60 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
61 "if run loadfdt; then " \
62 "bootz ${loadaddr} - ${fdt_addr}; " \
64 "if test ${boot_fdt} = try; then " \
67 "echo WARN: Cannot load the DT; " \
74 #define CONFIG_BOOTCOMMAND \
75 "mmc dev ${mmcdev};" \
76 "mmc dev ${mmcdev}; if mmc rescan; then " \
77 "if run loadbootscript; then " \
80 "if run loadimage; then " \
86 #define CONFIG_SYS_MEMTEST_START 0x80000000
87 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
89 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
90 #define CONFIG_SYS_HZ 1000
92 #define CONFIG_STACKSIZE SZ_128K
94 /* Physical Memory Map */
95 #define CONFIG_NR_DRAM_BANKS 1
96 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
98 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
99 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
100 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
102 #define CONFIG_SYS_INIT_SP_OFFSET \
103 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
104 #define CONFIG_SYS_INIT_SP_ADDR \
105 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
107 /* FLASH and environment organization */
108 #define CONFIG_SYS_NO_FLASH
109 #define CONFIG_ENV_SIZE SZ_8K
110 #define CONFIG_ENV_IS_IN_MMC
112 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
113 #define CONFIG_SYS_FSL_USDHC_NUM 1
115 #define CONFIG_SYS_MMC_ENV_DEV 0
116 #define CONFIG_SYS_MMC_ENV_PART 0
117 #define CONFIG_MMCROOT "/dev/mmcblk2p2"
120 #define CONFIG_USB_EHCI
121 #define CONFIG_USB_EHCI_MX7
122 #define CONFIG_USB_STORAGE
123 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
125 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
126 #define CONFIG_MXC_USB_FLAGS 0
127 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
129 #define CONFIG_IMX_THERMAL
131 #define CONFIG_CI_UDC
132 #define CONFIG_USBD_HS
133 #define CONFIG_USB_GADGET_DUALSPEED
135 #define CONFIG_USB_GADGET
136 #define CONFIG_USB_FUNCTION_MASS_STORAGE
137 #define CONFIG_USB_GADGET_DOWNLOAD
138 #define CONFIG_USB_GADGET_VBUS_DRAW 2
140 #define CONFIG_G_DNL_VENDOR_NUM 0x0525
141 #define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
142 #define CONFIG_G_DNL_MANUFACTURER "FSL"
144 /* USB Device Firmware Update support */
145 #define CONFIG_USB_FUNCTION_DFU
146 #define CONFIG_DFU_MMC
147 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
148 #define DFU_DEFAULT_POLL_TIMEOUT 300