2 * Copyright (C) 2016 NXP Semiconductors
4 * Configuration settings for the i.MX7S Warp board.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __WARP7_CONFIG_H
10 #define __WARP7_CONFIG_H
12 #include "mx7_common.h"
14 #define PHYS_SDRAM_SIZE SZ_512M
16 #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
18 /* Size of malloc() pool */
19 #define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M)
22 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
23 #define CONFIG_SUPPORT_EMMC_BOOT
24 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
25 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
27 #define CONFIG_DFU_ENV_SETTINGS \
28 "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \
30 #define CONFIG_EXTRA_ENV_SETTINGS \
31 CONFIG_DFU_ENV_SETTINGS \
35 "ethact=usb_ether\0" \
36 "fdt_high=0xffffffff\0" \
37 "initrd_high=0xffffffff\0" \
38 "fdt_file=imx7s-warp.dtb\0" \
39 "fdt_addr=0x83000000\0" \
42 "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
43 "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
44 "finduuid=part uuid mmc 0:2 uuid\0" \
45 "mmcargs=setenv bootargs console=${console},${baudrate} " \
46 "root=PARTUUID=${uuid} rootwait rw\0" \
48 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
49 "bootscript=echo Running bootscript from mmc ...; " \
51 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
52 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
53 "mmcboot=echo Booting from mmc ...; " \
56 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
57 "if run loadfdt; then " \
58 "bootz ${loadaddr} - ${fdt_addr}; " \
60 "if test ${boot_fdt} = try; then " \
63 "echo WARN: Cannot load the DT; " \
70 #define CONFIG_BOOTCOMMAND \
71 "mmc dev ${mmcdev};" \
72 "mmc dev ${mmcdev}; if mmc rescan; then " \
73 "if run loadbootscript; then " \
76 "if run loadimage; then " \
82 #define CONFIG_SYS_MEMTEST_START 0x80000000
83 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
85 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
86 #define CONFIG_SYS_HZ 1000
88 /* Physical Memory Map */
89 #define CONFIG_NR_DRAM_BANKS 1
90 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
92 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
93 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
94 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
96 #define CONFIG_SYS_INIT_SP_OFFSET \
97 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
98 #define CONFIG_SYS_INIT_SP_ADDR \
99 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
102 #define CONFIG_SYS_I2C
103 #define CONFIG_SYS_I2C_MXC
104 #define CONFIG_SYS_I2C_MXC_I2C1
105 #define CONFIG_SYS_I2C_SPEED 100000
109 #define CONFIG_POWER_I2C
110 #define CONFIG_POWER_PFUZE3000
111 #define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
113 /* environment organization */
114 #define CONFIG_ENV_SIZE SZ_8K
115 #define CONFIG_ENV_IS_IN_MMC
117 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
118 #define CONFIG_SYS_FSL_USDHC_NUM 1
120 #define CONFIG_SYS_MMC_ENV_DEV 0
121 #define CONFIG_SYS_MMC_ENV_PART 0
124 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
126 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
127 #define CONFIG_MXC_USB_FLAGS 0
128 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */
130 #define CONFIG_IMX_THERMAL
132 #define CONFIG_USBD_HS
134 #define CONFIG_USB_FUNCTION_MASS_STORAGE
136 /* USB Device Firmware Update support */
137 #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
138 #define DFU_DEFAULT_POLL_TIMEOUT 300
140 #define CONFIG_USB_ETHER
141 #define CONFIG_USB_ETH_CDC
142 #define CONFIG_USB_ETH_RNDIS
143 #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
144 #define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01"