include/configs/vpac270.h

   1 /*
   2  * Voipac PXA270 configuration file
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #ifndef __CONFIG_H
  23 #define __CONFIG_H
  24
  25 /*
  26  * High Level Board Configuration Options
  27  */
  28 #define CONFIG_PXA27X           1       /* Marvell PXA270 CPU */
  29 #define CONFIG_VPAC270          1       /* Voipac PXA270 board */
  30
  31 /*
  32  * Environment settings
  33  */
  34 #define CONFIG_ENV_OVERWRITE
  35 #define CONFIG_SYS_MALLOC_LEN           (128*1024)
  36 #define CONFIG_SYS_GBL_DATA_SIZE        128
  37
  38 #define CONFIG_BOOTCOMMAND                                              \
  39         "if mmc init && fatload mmc 0 0xa4000000 uImage; then "         \
  40                 "bootm 0xa4000000; "                                    \
  41         "fi; "                                                          \
  42         "if usb reset && fatload usb 0 0xa4000000 uImage; then "        \
  43                 "bootm 0xa4000000; "                                    \
  44         "fi; "                                                          \
  45         "if ide reset && fatload ide 0 0xa4000000 uImage; then "        \
  46                 "bootm 0xa4000000; "                                    \
  47         "fi; "                                                          \
  48         "bootm 0x60000;"
  49 #define CONFIG_BOOTARGS                 "console=tty0 console=ttyS0,115200"
  50 #define CONFIG_TIMESTAMP
  51 #define CONFIG_BOOTDELAY                2       /* Autoboot delay */
  52 #define CONFIG_CMDLINE_TAG
  53 #define CONFIG_SETUP_MEMORY_TAGS
  54
  55 #define CONFIG_LZMA                     /* LZMA compression support */
  56
  57 /*
  58  * Serial Console Configuration
  59  */
  60 #define CONFIG_PXA_SERIAL
  61 #define CONFIG_FFUART                   1
  62 #define CONFIG_BAUDRATE                 115200
  63 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  64
  65 /*
  66  * Bootloader Components Configuration
  67  */
  68 #include <config_cmd_default.h>
  69
  70 #define CONFIG_CMD_NET
  71 #define CONFIG_CMD_ENV
  72 #undef  CONFIG_CMD_IMLS
  73 #define CONFIG_CMD_MMC
  74 #define CONFIG_CMD_USB
  75 #undef  CONFIG_LCD
  76 #define CONFIG_CMD_IDE
  77
  78 #ifdef  CONFIG_ONENAND_U_BOOT
  79 #undef  CONFIG_CMD_FLASH
  80 #define CONFIG_CMD_ONENAND
  81 #else
  82 #define CONFIG_CMD_FLASH
  83 #undef  CONFIG_CMD_ONENAND
  84 #endif
  85
  86 /*
  87  * Networking Configuration
  88  *  chip on the Voipac PXA270 board
  89  */
  90 #ifdef  CONFIG_CMD_NET
  91 #define CONFIG_CMD_PING
  92 #define CONFIG_CMD_DHCP
  93
  94 #define CONFIG_NET_MULTI                1
  95 #define CONFIG_DRIVER_DM9000            1
  96 #define CONFIG_DM9000_BASE              0x08000300      /* CS2 */
  97 #define DM9000_IO                       (CONFIG_DM9000_BASE)
  98 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 4)
  99 #define CONFIG_NET_RETRY_COUNT          10
 100
 101 #define CONFIG_BOOTP_BOOTFILESIZE
 102 #define CONFIG_BOOTP_BOOTPATH
 103 #define CONFIG_BOOTP_GATEWAY
 104 #define CONFIG_BOOTP_HOSTNAME
 105 #endif
 106
 107 /*
 108  * MMC Card Configuration
 109  */
 110 #ifdef  CONFIG_CMD_MMC
 111 #define CONFIG_MMC
 112 #define CONFIG_PXA_MMC
 113 #define CONFIG_SYS_MMC_BASE             0xF0000000
 114 #define CONFIG_CMD_FAT
 115 #define CONFIG_CMD_EXT2
 116 #define CONFIG_DOS_PARTITION
 117 #endif
 118
 119 /*
 120  * KGDB
 121  */
 122 #ifdef  CONFIG_CMD_KGDB
 123 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
 124 #define CONFIG_KGDB_SER_INDEX           2       /* which serial port to use */
 125 #endif
 126
 127 /*
 128  * HUSH Shell Configuration
 129  */
 130 #define CONFIG_SYS_HUSH_PARSER          1
 131 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 132
 133 #define CONFIG_SYS_LONGHELP
 134 #ifdef  CONFIG_SYS_HUSH_PARSER
 135 #define CONFIG_SYS_PROMPT               "$ "
 136 #else
 137 #define CONFIG_SYS_PROMPT               "=> "
 138 #endif
 139 #define CONFIG_SYS_CBSIZE               256
 140 #define CONFIG_SYS_PBSIZE               \
 141         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 142 #define CONFIG_SYS_MAXARGS              16
 143 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 144 #define CONFIG_SYS_DEVICE_NULLDEV       1
 145
 146 /*
 147  * Clock Configuration
 148  */
 149 #define CONFIG_SYS_HZ                   1000            /* Timer @ 3250000 Hz */
 150 #define CONFIG_SYS_CPUSPEED             0x190           /* 312MHz */
 151
 152 /*
 153  * Stack sizes
 154  */
 155 #define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
 156 #ifdef  CONFIG_USE_IRQ
 157 #define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
 158 #define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
 159 #endif
 160
 161 /*
 162  * DRAM Map
 163  */
 164 #define CONFIG_NR_DRAM_BANKS            2               /* 2 banks of DRAM */
 165 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 166 #define PHYS_SDRAM_1_SIZE               0x08000000      /* 128 MB */
 167
 168 #ifdef  CONFIG_256M_U_BOOT
 169 #define PHYS_SDRAM_2                    0x80000000      /* SDRAM Bank #2 */
 170 #define PHYS_SDRAM_2_SIZE               0x08000000      /* 128 MB */
 171 #endif
 172
 173 #define CONFIG_SYS_DRAM_BASE            0xa0000000      /* CS0 */
 174 #ifdef  CONFIG_256M_U_BOOT
 175 #define CONFIG_SYS_DRAM_SIZE            0x10000000      /* 256 MB DRAM */
 176 #else
 177 #define CONFIG_SYS_DRAM_SIZE            0x08000000      /* 128 MB DRAM */
 178 #endif
 179
 180 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 181 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 182
 183 #define CONFIG_SYS_LOAD_ADDR            (0x5c000000)
 184
 185 /*
 186  * NOR FLASH
 187  */
 188 #define CONFIG_SYS_MONITOR_BASE         0x0
 189 #define CONFIG_SYS_MONITOR_LEN          0x40000
 190 #define CONFIG_ENV_ADDR                 \
 191                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 192 #define CONFIG_ENV_SIZE                 0x4000
 193
 194 #if     defined(CONFIG_CMD_FLASH)       /* NOR */
 195 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 196
 197 #ifdef  CONFIG_256M_U_BOOT
 198 #define PHYS_FLASH_2                    0x02000000      /* Flash Bank #2 */
 199 #endif
 200
 201 #define CONFIG_SYS_FLASH_CFI
 202 #define CONFIG_FLASH_CFI_DRIVER         1
 203
 204 #define CONFIG_SYS_MAX_FLASH_SECT       (4 + 255)
 205 #ifdef  CONFIG_256M_U_BOOT
 206 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 207 #define CONFIG_SYS_FLASH_BANKS_LIST     { PHYS_FLASH_1, PHYS_FLASH_2 }
 208 #else
 209 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 210 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 211 #endif
 212
 213 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ)
 214 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ)
 215
 216 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 217 #define CONFIG_SYS_FLASH_PROTECTION             1
 218
 219 #define CONFIG_ENV_IS_IN_FLASH          1
 220
 221 /*
 222  * The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the
 223  * flash consists of 0x20000 bytes big sectors.
 224  */
 225 #if     (CONFIG_ENV_ADDR <= 0x18000)
 226 #define CONFIG_ENV_SECT_SIZE            0x8000
 227 #else
 228 #define CONFIG_ENV_SECT_SIZE            0x20000
 229 #endif
 230
 231 #elif   defined(CONFIG_CMD_ONENAND)     /* OneNAND */
 232 #define CONFIG_SYS_NO_FLASH
 233 #define CONFIG_SYS_ONENAND_BASE         0x00000000
 234
 235 #define CONFIG_ENV_IS_IN_ONENAND        1
 236 #define CONFIG_ENV_SECT_SIZE            0x20000
 237
 238 #else   /* No flash */
 239 #define CONFIG_SYS_NO_FLASH
 240 #define CONFIG_SYS_ENV_IS_NOWHERE
 241 #endif
 242
 243 /*
 244  * IDE
 245  */
 246 #ifdef  CONFIG_CMD_IDE
 247 #define CONFIG_LBA48
 248 #undef  CONFIG_IDE_LED
 249 #undef  CONFIG_IDE_RESET
 250
 251 #define __io
 252
 253 #define CONFIG_SYS_IDE_MAXBUS           1
 254 #define CONFIG_SYS_IDE_MAXDEVICE        1
 255
 256 #define CONFIG_SYS_ATA_BASE_ADDR        0x0c000000
 257 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0
 258
 259 #define CONFIG_SYS_ATA_DATA_OFFSET      0x120
 260 #define CONFIG_SYS_ATA_REG_OFFSET       0x120
 261 #define CONFIG_SYS_ATA_ALT_OFFSET       0x120
 262
 263 #define CONFIG_SYS_ATA_STRIDE           2
 264 #endif
 265
 266 /*
 267  * GPIO settings
 268  */
 269 #define CONFIG_SYS_GPSR0_VAL    0x01308800
 270 #define CONFIG_SYS_GPSR1_VAL    0x00cf0000
 271 #define CONFIG_SYS_GPSR2_VAL    0x922ac000
 272 #define CONFIG_SYS_GPSR3_VAL    0x0161e800
 273
 274 #define CONFIG_SYS_GPCR0_VAL    0x00010000
 275 #define CONFIG_SYS_GPCR1_VAL    0x0
 276 #define CONFIG_SYS_GPCR2_VAL    0x0
 277 #define CONFIG_SYS_GPCR3_VAL    0x0
 278
 279 #define CONFIG_SYS_GPDR0_VAL    0xcbb18800
 280 #define CONFIG_SYS_GPDR1_VAL    0xfccfa981
 281 #define CONFIG_SYS_GPDR2_VAL    0x922affff
 282 #define CONFIG_SYS_GPDR3_VAL    0x0161e904
 283
 284 #define CONFIG_SYS_GAFR0_L_VAL  0x00100000
 285 #define CONFIG_SYS_GAFR0_U_VAL  0xa5da8510
 286 #define CONFIG_SYS_GAFR1_L_VAL  0x6992901a
 287 #define CONFIG_SYS_GAFR1_U_VAL  0xaaa5a0aa
 288 #define CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
 289 #define CONFIG_SYS_GAFR2_U_VAL  0x4109a401
 290 #define CONFIG_SYS_GAFR3_L_VAL  0x54010310
 291 #define CONFIG_SYS_GAFR3_U_VAL  0x00025401
 292
 293 #define CONFIG_SYS_PSSR_VAL     0x30
 294
 295 /*
 296  * Clock settings
 297  */
 298 #define CONFIG_SYS_CKEN         0x00500240
 299 #define CONFIG_SYS_CCCR         0x02000290
 300
 301 /*
 302  * Memory settings
 303  */
 304 #define CONFIG_SYS_MSC0_VAL     0x3ffc95fa
 305 #define CONFIG_SYS_MSC1_VAL     0x02ccf974
 306 #define CONFIG_SYS_MSC2_VAL     0x00000000
 307 #ifdef  CONFIG_256M_U_BOOT
 308 #define CONFIG_SYS_MDCNFG_VAL   0x8ad30ad3
 309 #else
 310 #define CONFIG_SYS_MDCNFG_VAL   0x88000ad3
 311 #endif
 312 #define CONFIG_SYS_MDREFR_VAL   0x201fe01e
 313 #define CONFIG_SYS_MDMRS_VAL    0x00000000
 314 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
 315 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 316 #define CONFIG_SYS_MEM_BUF_IMP  0x0f
 317
 318 /*
 319  * PCMCIA and CF Interfaces
 320  */
 321 #define CONFIG_SYS_MECR_VAL     0x00000001
 322 #define CONFIG_SYS_MCMEM0_VAL   0x00014307
 323 #define CONFIG_SYS_MCMEM1_VAL   0x00014307
 324 #define CONFIG_SYS_MCATT0_VAL   0x0001c787
 325 #define CONFIG_SYS_MCATT1_VAL   0x0001c787
 326 #define CONFIG_SYS_MCIO0_VAL    0x0001430f
 327 #define CONFIG_SYS_MCIO1_VAL    0x0001430f
 328
 329 /*
 330  * LCD
 331  */
 332 #ifdef  CONFIG_LCD
 333 #define CONFIG_VOIPAC_LCD
 334 #endif
 335
 336 /*
 337  * USB
 338  */
 339 #ifdef  CONFIG_CMD_USB
 340 #define CONFIG_USB_OHCI_NEW
 341 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 342 #define CONFIG_SYS_USB_OHCI_BOARD_INIT
 343 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 344 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x4C000000
 345 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "vpac270"
 346 #define CONFIG_USB_STORAGE
 347 #endif
 348
 349 #endif  /* __CONFIG_H */