include/configs/vme8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * esd vme8349 U-Boot configuration file
   4  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   5  *
   6  * (C) Copyright 2006-2010
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * reinhard.arlt@esd-electronics.de
  10  * Based on the MPC8349EMDS config.
  11  */
  12
  13 /*
  14  * vme8349 board configuration file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * Top level Makefile configuration choices
  22  */
  23 #ifdef CONFIG_CADDY2
  24 #define VME_CADDY2
  25 #endif
  26
  27 /*
  28  * High Level Configuration Options
  29  */
  30 #define CONFIG_E300             1       /* E300 Family */
  31
  32 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  33 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  34
  35 #define CONFIG_PCI_66M
  36 #ifdef CONFIG_PCI_66M
  37 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  38 #else
  39 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  40 #endif
  41
  42 #ifndef CONFIG_SYS_CLK_FREQ
  43 #ifdef CONFIG_PCI_66M
  44 #define CONFIG_SYS_CLK_FREQ     66000000
  45 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  46 #else
  47 #define CONFIG_SYS_CLK_FREQ     33000000
  48 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  49 #endif
  50 #endif
  51
  52 #define CONFIG_SYS_IMMR         0xE0000000
  53
  54 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  55 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  56 #define CONFIG_SYS_MEMTEST_END          0x00100000
  57
  58 /*
  59  * DDR Setup
  60  */
  61 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  62 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  63 #define CONFIG_SPD_EEPROM
  64 #define SPD_EEPROM_ADDRESS              0x54
  65 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  66 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  67
  68 /*
  69  * 32-bit data path mode.
  70  *
  71  * Please note that using this mode for devices with the real density of 64-bit
  72  * effectively reduces the amount of available memory due to the effect of
  73  * wrapping around while translating address to row/columns, for example in the
  74  * 256MB module the upper 128MB get aliased with contents of the lower
  75  * 128MB); normally this define should be used for devices with real 32-bit
  76  * data path.
  77  */
  78 #undef CONFIG_DDR_32BIT
  79
  80 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  81 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  82 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  83 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  84                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  85 #define CONFIG_DDR_2T_TIMING
  86 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  87                                         | DDRCDR_ODT \
  88                                         | DDRCDR_Q_DRN)
  89                                         /* 0x80080001 */
  90
  91 /*
  92  * FLASH on the Local Bus
  93  */
  94 #ifdef VME_CADDY2
  95 #define CONFIG_SYS_FLASH_BASE           0xffc00000      /* start of FLASH   */
  96 #define CONFIG_SYS_FLASH_SIZE           4               /* flash size in MB */
  97 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
  98                                          BR_PS_16 |     /*  16bit */ \
  99                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
 100                                          BR_V)          /* valid */
 101
 102 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 103                                         | OR_GPCM_XAM \
 104                                         | OR_GPCM_CSNT \
 105                                         | OR_GPCM_ACS_DIV2 \
 106                                         | OR_GPCM_XACS \
 107                                         | OR_GPCM_SCY_15 \
 108                                         | OR_GPCM_TRLX_SET \
 109                                         | OR_GPCM_EHTR_SET \
 110                                         | OR_GPCM_EAD)
 111                                         /* 0xffc06ff7 */
 112 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 113 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_4MB)
 114 #else
 115 #define CONFIG_SYS_FLASH_BASE           0xf8000000      /* start of FLASH   */
 116 #define CONFIG_SYS_FLASH_SIZE           128             /* flash size in MB */
 117 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
 118                                          BR_PS_16 |     /*  16bit */ \
 119                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
 120                                          BR_V)          /* valid */
 121
 122 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 123                                         | OR_GPCM_XAM \
 124                                         | OR_GPCM_CSNT \
 125                                         | OR_GPCM_ACS_DIV2 \
 126                                         | OR_GPCM_XACS \
 127                                         | OR_GPCM_SCY_15 \
 128                                         | OR_GPCM_TRLX_SET \
 129                                         | OR_GPCM_EHTR_SET \
 130                                         | OR_GPCM_EAD)
 131                                         /* 0xf8006ff7 */
 132 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 133 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 134 #endif
 135
 136 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
 137 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_WINDOW1_BASE \
 138                                         | BR_PS_32 \
 139                                         | BR_MS_GPCM \
 140                                         | BR_V)
 141                                         /* 0xF0001801 */
 142 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_256KB \
 143                                         | OR_GPCM_SETA)
 144                                         /* 0xfffc0208 */
 145 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_WINDOW1_BASE
 146 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_256KB)
 147
 148 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 149 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
 150
 151 #undef CONFIG_SYS_FLASH_CHECKSUM
 152 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
 153 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
 154
 155 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 156
 157 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 158 #define CONFIG_SYS_RAMBOOT
 159 #else
 160 #undef CONFIG_SYS_RAMBOOT
 161 #endif
 162
 163 #define CONFIG_SYS_INIT_RAM_LOCK        1
 164 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
 165 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
 166
 167 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 168                                          GENERATED_GBL_DATA_SIZE)
 169 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 170
 171 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
 172 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
 173
 174 /*
 175  * Local Bus LCRR and LBCR regs
 176  *    LCRR:  no DLL bypass, Clock divider is 4
 177  * External Local Bus rate is
 178  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 179  */
 180 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 181 #define CONFIG_SYS_LBC_LBCR     0x00000000
 182
 183 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 184
 185 /*
 186  * Serial Port
 187  */
 188 #define CONFIG_SYS_NS16550_SERIAL
 189 #define CONFIG_SYS_NS16550_REG_SIZE     1
 190 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 191
 192 #define CONFIG_SYS_BAUDRATE_TABLE  \
 193                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 194
 195 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 196 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 197
 198 /* I2C */
 199 #define CONFIG_SYS_I2C
 200 #define CONFIG_SYS_I2C_FSL
 201 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 202 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 203 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 204 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 205 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 206 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 207 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 208 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 209
 210 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 211
 212 /* TSEC */
 213 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 214 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 215 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 216 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 217
 218 /*
 219  * General PCI
 220  * Addresses are mapped 1-1.
 221  */
 222 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 223 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 224 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 225 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 226 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 227 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 228 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 229 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 230 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 231
 232 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 233 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 234 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 235 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 236 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 237 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 238 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 239 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 240 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 241
 242 #if defined(CONFIG_PCI)
 243
 244 #define PCI_64BIT
 245 #define PCI_ONE_PCI1
 246 #if defined(PCI_64BIT)
 247 #undef PCI_ALL_PCI1
 248 #undef PCI_TWO_PCI1
 249 #undef PCI_ONE_PCI1
 250 #endif
 251
 252 #undef CONFIG_EEPRO100
 253 #undef CONFIG_TULIP
 254
 255 #if !defined(CONFIG_PCI_PNP)
 256         #define PCI_ENET0_IOADDR        0xFIXME
 257         #define PCI_ENET0_MEMADDR       0xFIXME
 258         #define PCI_IDSEL_NUMBER        0xFIXME
 259 #endif
 260
 261 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 262 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 263
 264 #endif  /* CONFIG_PCI */
 265
 266 /*
 267  * TSEC configuration
 268  */
 269
 270 #if defined(CONFIG_TSEC_ENET)
 271
 272 #define CONFIG_GMII                     /* MII PHY management */
 273 #define CONFIG_TSEC1
 274 #define CONFIG_TSEC1_NAME       "TSEC0"
 275 #define CONFIG_TSEC2
 276 #define CONFIG_TSEC2_NAME       "TSEC1"
 277 #define CONFIG_PHY_M88E1111
 278 #define TSEC1_PHY_ADDR          0x08
 279 #define TSEC2_PHY_ADDR          0x10
 280 #define TSEC1_PHYIDX            0
 281 #define TSEC2_PHYIDX            0
 282 #define TSEC1_FLAGS             TSEC_GIGABIT
 283 #define TSEC2_FLAGS             TSEC_GIGABIT
 284
 285 /* Options are: TSEC[0-1] */
 286 #define CONFIG_ETHPRIME         "TSEC0"
 287
 288 #endif  /* CONFIG_TSEC_ENET */
 289
 290 /*
 291  * Environment
 292  */
 293 #ifndef CONFIG_SYS_RAMBOOT
 294         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0xc0000)
 295         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 296         #define CONFIG_ENV_SIZE         0x2000
 297
 298 /* Address and size of Redundant Environment Sector     */
 299 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 300 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 301
 302 #else
 303         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 304         #define CONFIG_ENV_SIZE         0x2000
 305 #endif
 306
 307 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 308 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 309
 310 /*
 311  * BOOTP options
 312  */
 313 #define CONFIG_BOOTP_BOOTFILESIZE
 314
 315 /*
 316  * Command line configuration.
 317  */
 318 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 319 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 320 #define CONFIG_RTC_RX8025
 321
 322 /* Pass Ethernet MAC to VxWorks */
 323 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 324
 325 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 326
 327 /*
 328  * Miscellaneous configurable options
 329  */
 330 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 331
 332 /*
 333  * For booting Linux, the board info and command line data
 334  * have to be in the first 256 MB of memory, since this is
 335  * the maximum mapped by the Linux kernel during initialization.
 336  */
 337 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 338
 339 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 340
 341 #define CONFIG_SYS_HRCW_LOW (\
 342         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 343         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 344         HRCWL_CSB_TO_CLKIN |\
 345         HRCWL_VCO_1X2 |\
 346         HRCWL_CORE_TO_CSB_2X1)
 347
 348 #if defined(PCI_64BIT)
 349 #define CONFIG_SYS_HRCW_HIGH (\
 350         HRCWH_PCI_HOST |\
 351         HRCWH_64_BIT_PCI |\
 352         HRCWH_PCI1_ARBITER_ENABLE |\
 353         HRCWH_PCI2_ARBITER_DISABLE |\
 354         HRCWH_CORE_ENABLE |\
 355         HRCWH_FROM_0X00000100 |\
 356         HRCWH_BOOTSEQ_DISABLE |\
 357         HRCWH_SW_WATCHDOG_DISABLE |\
 358         HRCWH_ROM_LOC_LOCAL_16BIT |\
 359         HRCWH_TSEC1M_IN_GMII |\
 360         HRCWH_TSEC2M_IN_GMII)
 361 #else
 362 #define CONFIG_SYS_HRCW_HIGH (\
 363         HRCWH_PCI_HOST |\
 364         HRCWH_32_BIT_PCI |\
 365         HRCWH_PCI1_ARBITER_ENABLE |\
 366         HRCWH_PCI2_ARBITER_ENABLE |\
 367         HRCWH_CORE_ENABLE |\
 368         HRCWH_FROM_0X00000100 |\
 369         HRCWH_BOOTSEQ_DISABLE |\
 370         HRCWH_SW_WATCHDOG_DISABLE |\
 371         HRCWH_ROM_LOC_LOCAL_16BIT |\
 372         HRCWH_TSEC1M_IN_GMII |\
 373         HRCWH_TSEC2M_IN_GMII)
 374 #endif
 375
 376 /* System IO Config */
 377 #define CONFIG_SYS_SICRH 0
 378 #define CONFIG_SYS_SICRL SICRL_LDP_A
 379
 380 #define CONFIG_SYS_HID0_INIT    0x000000000
 381 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 382                                  HID0_ENABLE_INSTRUCTION_CACHE)
 383
 384 #define CONFIG_SYS_HID2         HID2_HBE
 385
 386 #define CONFIG_SYS_GPIO1_PRELIM
 387 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 388 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 389
 390 #define CONFIG_SYS_GPIO2_PRELIM
 391 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 392 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 393
 394 #define CONFIG_HIGH_BATS                /* High BATs supported */
 395
 396 /* DDR @ 0x00000000 */
 397 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 398                                  BATL_MEMCOHERENCE)
 399 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 400                                  BATU_VS | BATU_VP)
 401
 402 /* PCI @ 0x80000000 */
 403 #ifdef CONFIG_PCI
 404 #define CONFIG_PCI_INDIRECT_BRIDGE
 405 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
 406                                  BATL_MEMCOHERENCE)
 407 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
 408                                  BATU_VS | BATU_VP)
 409 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
 410                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 411 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
 412                                  BATU_VS | BATU_VP)
 413 #else
 414 #define CONFIG_SYS_IBAT1L       (0)
 415 #define CONFIG_SYS_IBAT1U       (0)
 416 #define CONFIG_SYS_IBAT2L       (0)
 417 #define CONFIG_SYS_IBAT2U       (0)
 418 #endif
 419
 420 #ifdef CONFIG_MPC83XX_PCI2
 421 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
 422                                  BATL_MEMCOHERENCE)
 423 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
 424                                  BATU_VS | BATU_VP)
 425 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
 426                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 427 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
 428                                  BATU_VS | BATU_VP)
 429 #else
 430 #define CONFIG_SYS_IBAT3L       (0)
 431 #define CONFIG_SYS_IBAT3U       (0)
 432 #define CONFIG_SYS_IBAT4L       (0)
 433 #define CONFIG_SYS_IBAT4U       (0)
 434 #endif
 435
 436 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 437 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 438                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 439 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | \
 440                                  BATU_VS | BATU_VP)
 441
 442 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
 443 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 444
 445 #if (CONFIG_SYS_DDR_SIZE == 512)
 446 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 447                                  BATL_PP_RW | BATL_MEMCOHERENCE)
 448 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 449                                  BATU_BL_256M | BATU_VS | BATU_VP)
 450 #else
 451 #define CONFIG_SYS_IBAT7L       (0)
 452 #define CONFIG_SYS_IBAT7U       (0)
 453 #endif
 454
 455 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 456 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 457 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 458 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 459 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 460 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 461 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 462 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 463 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 464 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 465 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 466 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 467 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 468 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 469 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 470 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 471
 472 #if defined(CONFIG_CMD_KGDB)
 473 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 474 #endif
 475
 476 /*
 477  * Environment Configuration
 478  */
 479 #define CONFIG_ENV_OVERWRITE
 480
 481 #if defined(CONFIG_TSEC_ENET)
 482 #define CONFIG_HAS_ETH0
 483 #define CONFIG_HAS_ETH1
 484 #endif
 485
 486 #define CONFIG_HOSTNAME         "VME8349"
 487 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 488 #define CONFIG_BOOTFILE         "uImage"
 489
 490 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 491
 492 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 493         "netdev=eth0\0"                                                 \
 494         "hostname=vme8349\0"                                            \
 495         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 496                 "nfsroot=${serverip}:${rootpath}\0"                     \
 497         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 498         "addip=setenv bootargs ${bootargs} "                            \
 499                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 500                 ":${hostname}:${netdev}:off panic=1\0"                  \
 501         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 502         "flash_nfs=run nfsargs addip addtty;"                           \
 503                 "bootm ${kernel_addr}\0"                                \
 504         "flash_self=run ramargs addip addtty;"                          \
 505                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 506         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 507                 "bootm\0"                                               \
 508         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 509         "update=protect off fff00000 fff3ffff; "                        \
 510                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 511         "upd=run load update\0"                                         \
 512         "fdtaddr=780000\0"                                              \
 513         "fdtfile=vme8349.dtb\0"                                         \
 514         ""
 515
 516 #define CONFIG_NFSBOOTCOMMAND                                           \
 517         "setenv bootargs root=/dev/nfs rw "                             \
 518                 "nfsroot=$serverip:$rootpath "                          \
 519                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 520                                                         "$netdev:off "  \
 521                 "console=$consoledev,$baudrate $othbootargs;"           \
 522         "tftp $loadaddr $bootfile;"                                     \
 523         "tftp $fdtaddr $fdtfile;"                                       \
 524         "bootm $loadaddr - $fdtaddr"
 525
 526 #define CONFIG_RAMBOOTCOMMAND                                           \
 527         "setenv bootargs root=/dev/ram rw "                             \
 528                 "console=$consoledev,$baudrate $othbootargs;"           \
 529         "tftp $ramdiskaddr $ramdiskfile;"                               \
 530         "tftp $loadaddr $bootfile;"                                     \
 531         "tftp $fdtaddr $fdtfile;"                                       \
 532         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 533
 534 #define CONFIG_BOOTCOMMAND      "run flash_self"
 535
 536 #ifndef __ASSEMBLY__
 537 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 538                      unsigned char *buffer, int len);
 539 #endif
 540
 541 #endif  /* __CONFIG_H */