include/configs/vme8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * esd vme8349 U-Boot configuration file
   4  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   5  *
   6  * (C) Copyright 2006-2010
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * reinhard.arlt@esd-electronics.de
  10  * Based on the MPC8349EMDS config.
  11  */
  12
  13 /*
  14  * vme8349 board configuration file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_E300             1       /* E300 Family */
  24
  25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  26 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  27
  28 #define CONFIG_SYS_IMMR         0xE0000000
  29
  30 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  31 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  32 #define CONFIG_SYS_MEMTEST_END          0x00100000
  33
  34 /*
  35  * DDR Setup
  36  */
  37 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  38 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  39 #define CONFIG_SPD_EEPROM
  40 #define SPD_EEPROM_ADDRESS              0x54
  41 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  42 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  43
  44 /*
  45  * 32-bit data path mode.
  46  *
  47  * Please note that using this mode for devices with the real density of 64-bit
  48  * effectively reduces the amount of available memory due to the effect of
  49  * wrapping around while translating address to row/columns, for example in the
  50  * 256MB module the upper 128MB get aliased with contents of the lower
  51  * 128MB); normally this define should be used for devices with real 32-bit
  52  * data path.
  53  */
  54 #undef CONFIG_DDR_32BIT
  55
  56 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  57 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  58 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  59 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  60                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  61 #define CONFIG_DDR_2T_TIMING
  62 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  63                                         | DDRCDR_ODT \
  64                                         | DDRCDR_Q_DRN)
  65                                         /* 0x80080001 */
  66
  67 /*
  68  * FLASH on the Local Bus
  69  */
  70 #define CONFIG_SYS_FLASH_BASE           0xf8000000      /* start of FLASH   */
  71 #define CONFIG_SYS_FLASH_SIZE           128             /* flash size in MB */
  72
  73 /* FLASH */
  74 #define CONFIG_SYS_BR0_PRELIM           (0xF8000000 | BR_PS_16 | BR_MS_GPCM | BR_V)
  75 #define CONFIG_SYS_OR0_PRELIM           (OR_AM_128MB | OR_GPCM_XAM | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD)
  76
  77 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
  78
  79 /* WINDOW1 */
  80 #define CONFIG_SYS_BR1_PRELIM           (0xF0000000 | BR_PS_32 | BR_MS_GPCM | BR_V)
  81 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_256KB | OR_GPCM_SETA)
  82
  83 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  84 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
  85
  86 #undef CONFIG_SYS_FLASH_CHECKSUM
  87 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
  88 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
  89
  90 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  91
  92 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  93 #define CONFIG_SYS_RAMBOOT
  94 #else
  95 #undef CONFIG_SYS_RAMBOOT
  96 #endif
  97
  98 #define CONFIG_SYS_INIT_RAM_LOCK        1
  99 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
 100 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
 101
 102 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 103                                          GENERATED_GBL_DATA_SIZE)
 104 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 105
 106 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
 107 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
 108
 109 /*
 110  * Local Bus LCRR and LBCR regs
 111  *    LCRR:  no DLL bypass, Clock divider is 4
 112  * External Local Bus rate is
 113  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 114  */
 115 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 116 #define CONFIG_SYS_LBC_LBCR     0x00000000
 117
 118 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 119
 120 /*
 121  * Serial Port
 122  */
 123 #define CONFIG_SYS_NS16550_SERIAL
 124 #define CONFIG_SYS_NS16550_REG_SIZE     1
 125 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 126
 127 #define CONFIG_SYS_BAUDRATE_TABLE  \
 128                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 129
 130 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 131 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 132
 133 /* I2C */
 134 #define CONFIG_SYS_I2C
 135 #define CONFIG_SYS_I2C_FSL
 136 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 137 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 138 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 139 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 140 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 141 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 142 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 143 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 144
 145 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 146
 147 /* TSEC */
 148 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 149 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 150 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 151 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 152
 153 /*
 154  * General PCI
 155  * Addresses are mapped 1-1.
 156  */
 157 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 158 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 159 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 160 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 161 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 162 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 163 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 164 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 165 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 166
 167 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 168 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 169 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 170 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 171 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 172 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 173 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 174 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 175 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 176
 177 #if defined(CONFIG_PCI)
 178
 179 #undef CONFIG_EEPRO100
 180 #undef CONFIG_TULIP
 181
 182 #if !defined(CONFIG_PCI_PNP)
 183         #define PCI_ENET0_IOADDR        0xFIXME
 184         #define PCI_ENET0_MEMADDR       0xFIXME
 185         #define PCI_IDSEL_NUMBER        0xFIXME
 186 #endif
 187
 188 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 189 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 190
 191 #endif  /* CONFIG_PCI */
 192
 193 /*
 194  * TSEC configuration
 195  */
 196
 197 #if defined(CONFIG_TSEC_ENET)
 198
 199 #define CONFIG_GMII                     /* MII PHY management */
 200 #define CONFIG_TSEC1
 201 #define CONFIG_TSEC1_NAME       "TSEC0"
 202 #define CONFIG_TSEC2
 203 #define CONFIG_TSEC2_NAME       "TSEC1"
 204 #define CONFIG_PHY_M88E1111
 205 #define TSEC1_PHY_ADDR          0x08
 206 #define TSEC2_PHY_ADDR          0x10
 207 #define TSEC1_PHYIDX            0
 208 #define TSEC2_PHYIDX            0
 209 #define TSEC1_FLAGS             TSEC_GIGABIT
 210 #define TSEC2_FLAGS             TSEC_GIGABIT
 211
 212 /* Options are: TSEC[0-1] */
 213 #define CONFIG_ETHPRIME         "TSEC0"
 214
 215 #endif  /* CONFIG_TSEC_ENET */
 216
 217 /*
 218  * Environment
 219  */
 220 #ifndef CONFIG_SYS_RAMBOOT
 221         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0xc0000)
 222         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 223         #define CONFIG_ENV_SIZE         0x2000
 224
 225 /* Address and size of Redundant Environment Sector     */
 226 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 227 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 228
 229 #else
 230         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 231         #define CONFIG_ENV_SIZE         0x2000
 232 #endif
 233
 234 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 235 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 236
 237 /*
 238  * BOOTP options
 239  */
 240 #define CONFIG_BOOTP_BOOTFILESIZE
 241
 242 /*
 243  * Command line configuration.
 244  */
 245 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 246 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 247 #define CONFIG_RTC_RX8025
 248
 249 /* Pass Ethernet MAC to VxWorks */
 250 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 251
 252 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 253
 254 /*
 255  * Miscellaneous configurable options
 256  */
 257 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 258
 259 /*
 260  * For booting Linux, the board info and command line data
 261  * have to be in the first 256 MB of memory, since this is
 262  * the maximum mapped by the Linux kernel during initialization.
 263  */
 264 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 265
 266 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 267
 268 /* System IO Config */
 269 #define CONFIG_SYS_SICRH 0
 270 #define CONFIG_SYS_SICRL SICRL_LDP_A
 271
 272 #define CONFIG_SYS_HID0_INIT    0x000000000
 273 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 274                                  HID0_ENABLE_INSTRUCTION_CACHE)
 275
 276 #define CONFIG_SYS_HID2         HID2_HBE
 277
 278 #define CONFIG_SYS_GPIO1_PRELIM
 279 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 280 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 281
 282 #define CONFIG_SYS_GPIO2_PRELIM
 283 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 284 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 285
 286 #ifdef CONFIG_PCI
 287 #define CONFIG_PCI_INDIRECT_BRIDGE
 288 #endif
 289
 290 #if defined(CONFIG_CMD_KGDB)
 291 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 292 #endif
 293
 294 /*
 295  * Environment Configuration
 296  */
 297 #define CONFIG_ENV_OVERWRITE
 298
 299 #if defined(CONFIG_TSEC_ENET)
 300 #define CONFIG_HAS_ETH0
 301 #define CONFIG_HAS_ETH1
 302 #endif
 303
 304 #define CONFIG_HOSTNAME         "VME8349"
 305 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 306 #define CONFIG_BOOTFILE         "uImage"
 307
 308 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 309
 310 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 311         "netdev=eth0\0"                                                 \
 312         "hostname=vme8349\0"                                            \
 313         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 314                 "nfsroot=${serverip}:${rootpath}\0"                     \
 315         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 316         "addip=setenv bootargs ${bootargs} "                            \
 317                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 318                 ":${hostname}:${netdev}:off panic=1\0"                  \
 319         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 320         "flash_nfs=run nfsargs addip addtty;"                           \
 321                 "bootm ${kernel_addr}\0"                                \
 322         "flash_self=run ramargs addip addtty;"                          \
 323                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 324         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 325                 "bootm\0"                                               \
 326         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 327         "update=protect off fff00000 fff3ffff; "                        \
 328                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 329         "upd=run load update\0"                                         \
 330         "fdtaddr=780000\0"                                              \
 331         "fdtfile=vme8349.dtb\0"                                         \
 332         ""
 333
 334 #define CONFIG_NFSBOOTCOMMAND                                           \
 335         "setenv bootargs root=/dev/nfs rw "                             \
 336                 "nfsroot=$serverip:$rootpath "                          \
 337                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 338                                                         "$netdev:off "  \
 339                 "console=$consoledev,$baudrate $othbootargs;"           \
 340         "tftp $loadaddr $bootfile;"                                     \
 341         "tftp $fdtaddr $fdtfile;"                                       \
 342         "bootm $loadaddr - $fdtaddr"
 343
 344 #define CONFIG_RAMBOOTCOMMAND                                           \
 345         "setenv bootargs root=/dev/ram rw "                             \
 346                 "console=$consoledev,$baudrate $othbootargs;"           \
 347         "tftp $ramdiskaddr $ramdiskfile;"                               \
 348         "tftp $loadaddr $bootfile;"                                     \
 349         "tftp $fdtaddr $fdtfile;"                                       \
 350         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 351
 352 #define CONFIG_BOOTCOMMAND      "run flash_self"
 353
 354 #ifndef __ASSEMBLY__
 355 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 356                      unsigned char *buffer, int len);
 357 #endif
 358
 359 #endif  /* __CONFIG_H */