2 * esd vme8349 U-Boot configuration file
3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
5 * (C) Copyright 2006-2010
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * reinhard.arlt@esd-electronics.de
9 * Based on the MPC8349EMDS config.
11 * SPDX-License-Identifier: GPL-2.0+
15 * vme8349 board configuration file.
22 * Top level Makefile configuration choices
29 * High Level Configuration Options
31 #define CONFIG_E300 1 /* E300 Family */
32 #define CONFIG_MPC834x 1 /* MPC834x family */
33 #define CONFIG_MPC8349 1 /* MPC8349 specific */
34 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */
36 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
38 #define CONFIG_MISC_INIT_R
40 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
41 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
43 #define CONFIG_PCI_66M
45 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
47 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
50 #ifndef CONFIG_SYS_CLK_FREQ
52 #define CONFIG_SYS_CLK_FREQ 66000000
53 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
55 #define CONFIG_SYS_CLK_FREQ 33000000
56 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
60 #define CONFIG_SYS_IMMR 0xE0000000
62 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
63 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
64 #define CONFIG_SYS_MEMTEST_END 0x00100000
69 #define CONFIG_DDR_ECC /* only for ECC DDR module */
70 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
71 #define CONFIG_SPD_EEPROM
72 #define SPD_EEPROM_ADDRESS 0x54
73 #define CONFIG_SYS_READ_SPD vme8349_read_spd
74 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
77 * 32-bit data path mode.
79 * Please note that using this mode for devices with the real density of 64-bit
80 * effectively reduces the amount of available memory due to the effect of
81 * wrapping around while translating address to row/columns, for example in the
82 * 256MB module the upper 128MB get aliased with contents of the lower
83 * 128MB); normally this define should be used for devices with real 32-bit
86 #undef CONFIG_DDR_32BIT
88 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
89 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
90 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
91 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
92 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
93 #define CONFIG_DDR_2T_TIMING
94 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
100 * FLASH on the Local Bus
102 #define CONFIG_SYS_FLASH_CFI
103 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
105 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
106 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
107 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
108 BR_PS_16 | /* 16bit */ \
109 BR_MS_GPCM | /* MSEL = GPCM */ \
112 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
122 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
123 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
125 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
126 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
127 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
128 BR_PS_16 | /* 16bit */ \
129 BR_MS_GPCM | /* MSEL = GPCM */ \
132 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
142 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
143 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
145 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
147 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
148 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
153 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
156 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
157 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
159 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
160 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
162 #undef CONFIG_SYS_FLASH_CHECKSUM
163 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
164 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
166 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
168 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
169 #define CONFIG_SYS_RAMBOOT
171 #undef CONFIG_SYS_RAMBOOT
174 #define CONFIG_SYS_INIT_RAM_LOCK 1
175 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
176 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
178 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
179 GENERATED_GBL_DATA_SIZE)
180 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
182 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
183 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
186 * Local Bus LCRR and LBCR regs
187 * LCRR: no DLL bypass, Clock divider is 4
188 * External Local Bus rate is
189 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
191 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
192 #define CONFIG_SYS_LBC_LBCR 0x00000000
194 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
199 #define CONFIG_CONS_INDEX 1
200 #define CONFIG_SYS_NS16550_SERIAL
201 #define CONFIG_SYS_NS16550_REG_SIZE 1
202 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
204 #define CONFIG_SYS_BAUDRATE_TABLE \
205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
207 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
208 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
210 #define CONFIG_CMDLINE_EDITING /* add command line history */
211 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
214 #define CONFIG_SYS_I2C
215 #define CONFIG_SYS_I2C_FSL
216 #define CONFIG_SYS_FSL_I2C_SPEED 400000
217 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
218 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
219 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
220 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
221 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
222 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
223 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
225 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
228 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
229 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
230 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
231 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
235 * Addresses are mapped 1-1.
237 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
238 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
239 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
240 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
241 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
242 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
243 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
244 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
245 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
247 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
248 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
249 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
250 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
251 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
252 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
253 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
254 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
255 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
257 #if defined(CONFIG_PCI)
261 #if defined(PCI_64BIT)
270 #undef CONFIG_EEPRO100
273 #if !defined(CONFIG_PCI_PNP)
274 #define PCI_ENET0_IOADDR 0xFIXME
275 #define PCI_ENET0_MEMADDR 0xFIXME
276 #define PCI_IDSEL_NUMBER 0xFIXME
279 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
280 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
282 #endif /* CONFIG_PCI */
289 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
292 #if defined(CONFIG_TSEC_ENET)
294 #define CONFIG_GMII /* MII PHY management */
296 #define CONFIG_TSEC1_NAME "TSEC0"
298 #define CONFIG_TSEC2_NAME "TSEC1"
299 #define CONFIG_PHY_M88E1111
300 #define TSEC1_PHY_ADDR 0x08
301 #define TSEC2_PHY_ADDR 0x10
302 #define TSEC1_PHYIDX 0
303 #define TSEC2_PHYIDX 0
304 #define TSEC1_FLAGS TSEC_GIGABIT
305 #define TSEC2_FLAGS TSEC_GIGABIT
307 /* Options are: TSEC[0-1] */
308 #define CONFIG_ETHPRIME "TSEC0"
310 #endif /* CONFIG_TSEC_ENET */
315 #ifndef CONFIG_SYS_RAMBOOT
316 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
317 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
318 #define CONFIG_ENV_SIZE 0x2000
320 /* Address and size of Redundant Environment Sector */
321 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
322 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
325 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
326 #define CONFIG_ENV_SIZE 0x2000
329 #define CONFIG_LOADS_ECHO /* echo on for serial download */
330 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
335 #define CONFIG_BOOTP_BOOTFILESIZE
336 #define CONFIG_BOOTP_BOOTPATH
337 #define CONFIG_BOOTP_GATEWAY
338 #define CONFIG_BOOTP_HOSTNAME
341 * Command line configuration.
343 #define CONFIG_SYS_RTC_BUS_NUM 0x01
344 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
345 #define CONFIG_RTC_RX8025
347 /* Pass Ethernet MAC to VxWorks */
348 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
350 #undef CONFIG_WATCHDOG /* watchdog disabled */
353 * Miscellaneous configurable options
355 #define CONFIG_SYS_LONGHELP /* undef to save memory */
356 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
359 * For booting Linux, the board info and command line data
360 * have to be in the first 256 MB of memory, since this is
361 * the maximum mapped by the Linux kernel during initialization.
363 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
365 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
367 #define CONFIG_SYS_HRCW_LOW (\
368 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
369 HRCWL_DDR_TO_SCB_CLK_1X1 |\
370 HRCWL_CSB_TO_CLKIN |\
372 HRCWL_CORE_TO_CSB_2X1)
374 #if defined(PCI_64BIT)
375 #define CONFIG_SYS_HRCW_HIGH (\
378 HRCWH_PCI1_ARBITER_ENABLE |\
379 HRCWH_PCI2_ARBITER_DISABLE |\
381 HRCWH_FROM_0X00000100 |\
382 HRCWH_BOOTSEQ_DISABLE |\
383 HRCWH_SW_WATCHDOG_DISABLE |\
384 HRCWH_ROM_LOC_LOCAL_16BIT |\
385 HRCWH_TSEC1M_IN_GMII |\
386 HRCWH_TSEC2M_IN_GMII)
388 #define CONFIG_SYS_HRCW_HIGH (\
391 HRCWH_PCI1_ARBITER_ENABLE |\
392 HRCWH_PCI2_ARBITER_ENABLE |\
394 HRCWH_FROM_0X00000100 |\
395 HRCWH_BOOTSEQ_DISABLE |\
396 HRCWH_SW_WATCHDOG_DISABLE |\
397 HRCWH_ROM_LOC_LOCAL_16BIT |\
398 HRCWH_TSEC1M_IN_GMII |\
399 HRCWH_TSEC2M_IN_GMII)
402 /* System IO Config */
403 #define CONFIG_SYS_SICRH 0
404 #define CONFIG_SYS_SICRL SICRL_LDP_A
406 #define CONFIG_SYS_HID0_INIT 0x000000000
407 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
408 HID0_ENABLE_INSTRUCTION_CACHE)
410 #define CONFIG_SYS_HID2 HID2_HBE
412 #define CONFIG_SYS_GPIO1_PRELIM
413 #define CONFIG_SYS_GPIO1_DIR 0x00100000
414 #define CONFIG_SYS_GPIO1_DAT 0x00100000
416 #define CONFIG_SYS_GPIO2_PRELIM
417 #define CONFIG_SYS_GPIO2_DIR 0x78900000
418 #define CONFIG_SYS_GPIO2_DAT 0x70100000
420 #define CONFIG_HIGH_BATS /* High BATs supported */
422 /* DDR @ 0x00000000 */
423 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
425 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
428 /* PCI @ 0x80000000 */
430 #define CONFIG_PCI_INDIRECT_BRIDGE
431 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
433 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
435 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
436 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
437 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
440 #define CONFIG_SYS_IBAT1L (0)
441 #define CONFIG_SYS_IBAT1U (0)
442 #define CONFIG_SYS_IBAT2L (0)
443 #define CONFIG_SYS_IBAT2U (0)
446 #ifdef CONFIG_MPC83XX_PCI2
447 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
449 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
451 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
452 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
453 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
456 #define CONFIG_SYS_IBAT3L (0)
457 #define CONFIG_SYS_IBAT3U (0)
458 #define CONFIG_SYS_IBAT4L (0)
459 #define CONFIG_SYS_IBAT4U (0)
462 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
463 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
464 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
465 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
468 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
469 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
471 #if (CONFIG_SYS_DDR_SIZE == 512)
472 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
473 BATL_PP_RW | BATL_MEMCOHERENCE)
474 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
475 BATU_BL_256M | BATU_VS | BATU_VP)
477 #define CONFIG_SYS_IBAT7L (0)
478 #define CONFIG_SYS_IBAT7U (0)
481 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
482 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
483 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
484 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
485 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
486 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
487 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
488 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
489 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
490 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
491 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
492 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
493 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
494 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
495 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
496 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
498 #if defined(CONFIG_CMD_KGDB)
499 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
503 * Environment Configuration
505 #define CONFIG_ENV_OVERWRITE
507 #if defined(CONFIG_TSEC_ENET)
508 #define CONFIG_HAS_ETH0
509 #define CONFIG_HAS_ETH1
512 #define CONFIG_HOSTNAME VME8349
513 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
514 #define CONFIG_BOOTFILE "uImage"
516 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
518 #define CONFIG_EXTRA_ENV_SETTINGS \
520 "hostname=vme8349\0" \
521 "nfsargs=setenv bootargs root=/dev/nfs rw " \
522 "nfsroot=${serverip}:${rootpath}\0" \
523 "ramargs=setenv bootargs root=/dev/ram rw\0" \
524 "addip=setenv bootargs ${bootargs} " \
525 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
526 ":${hostname}:${netdev}:off panic=1\0" \
527 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
528 "flash_nfs=run nfsargs addip addtty;" \
529 "bootm ${kernel_addr}\0" \
530 "flash_self=run ramargs addip addtty;" \
531 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
532 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
534 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
535 "update=protect off fff00000 fff3ffff; " \
536 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
537 "upd=run load update\0" \
539 "fdtfile=vme8349.dtb\0" \
542 #define CONFIG_NFSBOOTCOMMAND \
543 "setenv bootargs root=/dev/nfs rw " \
544 "nfsroot=$serverip:$rootpath " \
545 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
547 "console=$consoledev,$baudrate $othbootargs;" \
548 "tftp $loadaddr $bootfile;" \
549 "tftp $fdtaddr $fdtfile;" \
550 "bootm $loadaddr - $fdtaddr"
552 #define CONFIG_RAMBOOTCOMMAND \
553 "setenv bootargs root=/dev/ram rw " \
554 "console=$consoledev,$baudrate $othbootargs;" \
555 "tftp $ramdiskaddr $ramdiskfile;" \
556 "tftp $loadaddr $bootfile;" \
557 "tftp $fdtaddr $fdtfile;" \
558 "bootm $loadaddr $ramdiskaddr $fdtaddr"
560 #define CONFIG_BOOTCOMMAND "run flash_self"
563 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
564 unsigned char *buffer, int len);
567 #endif /* __CONFIG_H */