2 * esd vme8349 U-Boot configuration file
3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
5 * (C) Copyright 2006-2010
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * reinhard.arlt@esd-electronics.de
9 * Based on the MPC8349EMDS config.
11 * SPDX-License-Identifier: GPL-2.0+
15 * vme8349 board configuration file.
22 * Top level Makefile configuration choices
29 * High Level Configuration Options
31 #define CONFIG_E300 1 /* E300 Family */
32 #define CONFIG_MPC834x 1 /* MPC834x family */
33 #define CONFIG_MPC8349 1 /* MPC8349 specific */
34 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */
36 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
38 #define CONFIG_MISC_INIT_R
41 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
42 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
44 #define CONFIG_PCI_66M
46 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
48 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
51 #ifndef CONFIG_SYS_CLK_FREQ
53 #define CONFIG_SYS_CLK_FREQ 66000000
54 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
56 #define CONFIG_SYS_CLK_FREQ 33000000
57 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
61 #define CONFIG_SYS_IMMR 0xE0000000
63 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
64 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
65 #define CONFIG_SYS_MEMTEST_END 0x00100000
70 #define CONFIG_DDR_ECC /* only for ECC DDR module */
71 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
72 #define CONFIG_SPD_EEPROM
73 #define SPD_EEPROM_ADDRESS 0x54
74 #define CONFIG_SYS_READ_SPD vme8349_read_spd
75 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
78 * 32-bit data path mode.
80 * Please note that using this mode for devices with the real density of 64-bit
81 * effectively reduces the amount of available memory due to the effect of
82 * wrapping around while translating address to row/columns, for example in the
83 * 256MB module the upper 128MB get aliased with contents of the lower
84 * 128MB); normally this define should be used for devices with real 32-bit
87 #undef CONFIG_DDR_32BIT
89 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
90 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
91 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
92 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
93 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
94 #define CONFIG_DDR_2T_TIMING
95 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
101 * FLASH on the Local Bus
103 #define CONFIG_SYS_FLASH_CFI
104 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
106 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
107 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
108 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
109 BR_PS_16 | /* 16bit */ \
110 BR_MS_GPCM | /* MSEL = GPCM */ \
113 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
123 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
124 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
126 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
127 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
128 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
129 BR_PS_16 | /* 16bit */ \
130 BR_MS_GPCM | /* MSEL = GPCM */ \
133 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
143 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
144 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
146 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
148 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
149 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
154 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
157 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
158 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
160 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
161 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
163 #undef CONFIG_SYS_FLASH_CHECKSUM
164 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
167 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
169 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
170 #define CONFIG_SYS_RAMBOOT
172 #undef CONFIG_SYS_RAMBOOT
175 #define CONFIG_SYS_INIT_RAM_LOCK 1
176 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
177 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
179 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
180 GENERATED_GBL_DATA_SIZE)
181 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
183 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
184 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
187 * Local Bus LCRR and LBCR regs
188 * LCRR: no DLL bypass, Clock divider is 4
189 * External Local Bus rate is
190 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
192 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
193 #define CONFIG_SYS_LBC_LBCR 0x00000000
195 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
200 #define CONFIG_CONS_INDEX 1
201 #define CONFIG_SYS_NS16550_SERIAL
202 #define CONFIG_SYS_NS16550_REG_SIZE 1
203 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
205 #define CONFIG_SYS_BAUDRATE_TABLE \
206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
208 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
209 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
211 #define CONFIG_CMDLINE_EDITING /* add command line history */
212 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
215 #define CONFIG_SYS_I2C
216 #define CONFIG_SYS_I2C_FSL
217 #define CONFIG_SYS_FSL_I2C_SPEED 400000
218 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
219 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
220 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
221 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
222 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
223 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
224 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
226 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
229 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
230 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
231 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
232 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
236 * Addresses are mapped 1-1.
238 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
239 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
240 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
241 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
242 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
243 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
244 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
245 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
246 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
248 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
249 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
250 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
251 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
252 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
253 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
254 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
255 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
256 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
258 #if defined(CONFIG_PCI)
262 #if defined(PCI_64BIT)
270 #define CONFIG_PCI_PNP /* do pci plug-and-play */
272 #undef CONFIG_EEPRO100
275 #if !defined(CONFIG_PCI_PNP)
276 #define PCI_ENET0_IOADDR 0xFIXME
277 #define PCI_ENET0_MEMADDR 0xFIXME
278 #define PCI_IDSEL_NUMBER 0xFIXME
281 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
282 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
284 #endif /* CONFIG_PCI */
291 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
294 #if defined(CONFIG_TSEC_ENET)
296 #define CONFIG_GMII /* MII PHY management */
298 #define CONFIG_TSEC1_NAME "TSEC0"
300 #define CONFIG_TSEC2_NAME "TSEC1"
301 #define CONFIG_PHY_M88E1111
302 #define TSEC1_PHY_ADDR 0x08
303 #define TSEC2_PHY_ADDR 0x10
304 #define TSEC1_PHYIDX 0
305 #define TSEC2_PHYIDX 0
306 #define TSEC1_FLAGS TSEC_GIGABIT
307 #define TSEC2_FLAGS TSEC_GIGABIT
309 /* Options are: TSEC[0-1] */
310 #define CONFIG_ETHPRIME "TSEC0"
312 #endif /* CONFIG_TSEC_ENET */
317 #ifndef CONFIG_SYS_RAMBOOT
318 #define CONFIG_ENV_IS_IN_FLASH
319 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
320 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
321 #define CONFIG_ENV_SIZE 0x2000
323 /* Address and size of Redundant Environment Sector */
324 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
325 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
328 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
329 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
330 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
331 #define CONFIG_ENV_SIZE 0x2000
334 #define CONFIG_LOADS_ECHO /* echo on for serial download */
335 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
340 #define CONFIG_BOOTP_BOOTFILESIZE
341 #define CONFIG_BOOTP_BOOTPATH
342 #define CONFIG_BOOTP_GATEWAY
343 #define CONFIG_BOOTP_HOSTNAME
346 * Command line configuration.
348 #define CONFIG_CMD_DATE
349 #define CONFIG_SYS_RTC_BUS_NUM 0x01
350 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
351 #define CONFIG_RTC_RX8025
352 #define CONFIG_CMD_TSI148
354 #if defined(CONFIG_PCI)
355 #define CONFIG_CMD_PCI
358 #if defined(CONFIG_SYS_RAMBOOT)
359 #undef CONFIG_CMD_ENV
362 /* Pass Ethernet MAC to VxWorks */
363 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
365 #undef CONFIG_WATCHDOG /* watchdog disabled */
368 * Miscellaneous configurable options
370 #define CONFIG_SYS_LONGHELP /* undef to save memory */
371 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
373 #if defined(CONFIG_CMD_KGDB)
374 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
376 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
379 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
380 #define CONFIG_SYS_MAXARGS 16 /* max num of command args */
381 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
384 * For booting Linux, the board info and command line data
385 * have to be in the first 256 MB of memory, since this is
386 * the maximum mapped by the Linux kernel during initialization.
388 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
390 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
392 #define CONFIG_SYS_HRCW_LOW (\
393 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
394 HRCWL_DDR_TO_SCB_CLK_1X1 |\
395 HRCWL_CSB_TO_CLKIN |\
397 HRCWL_CORE_TO_CSB_2X1)
399 #if defined(PCI_64BIT)
400 #define CONFIG_SYS_HRCW_HIGH (\
403 HRCWH_PCI1_ARBITER_ENABLE |\
404 HRCWH_PCI2_ARBITER_DISABLE |\
406 HRCWH_FROM_0X00000100 |\
407 HRCWH_BOOTSEQ_DISABLE |\
408 HRCWH_SW_WATCHDOG_DISABLE |\
409 HRCWH_ROM_LOC_LOCAL_16BIT |\
410 HRCWH_TSEC1M_IN_GMII |\
411 HRCWH_TSEC2M_IN_GMII)
413 #define CONFIG_SYS_HRCW_HIGH (\
416 HRCWH_PCI1_ARBITER_ENABLE |\
417 HRCWH_PCI2_ARBITER_ENABLE |\
419 HRCWH_FROM_0X00000100 |\
420 HRCWH_BOOTSEQ_DISABLE |\
421 HRCWH_SW_WATCHDOG_DISABLE |\
422 HRCWH_ROM_LOC_LOCAL_16BIT |\
423 HRCWH_TSEC1M_IN_GMII |\
424 HRCWH_TSEC2M_IN_GMII)
427 /* System IO Config */
428 #define CONFIG_SYS_SICRH 0
429 #define CONFIG_SYS_SICRL SICRL_LDP_A
431 #define CONFIG_SYS_HID0_INIT 0x000000000
432 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
433 HID0_ENABLE_INSTRUCTION_CACHE)
435 #define CONFIG_SYS_HID2 HID2_HBE
437 #define CONFIG_SYS_GPIO1_PRELIM
438 #define CONFIG_SYS_GPIO1_DIR 0x00100000
439 #define CONFIG_SYS_GPIO1_DAT 0x00100000
441 #define CONFIG_SYS_GPIO2_PRELIM
442 #define CONFIG_SYS_GPIO2_DIR 0x78900000
443 #define CONFIG_SYS_GPIO2_DAT 0x70100000
445 #define CONFIG_HIGH_BATS /* High BATs supported */
447 /* DDR @ 0x00000000 */
448 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
450 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
453 /* PCI @ 0x80000000 */
455 #define CONFIG_PCI_INDIRECT_BRIDGE
456 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
458 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
460 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
461 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
462 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
465 #define CONFIG_SYS_IBAT1L (0)
466 #define CONFIG_SYS_IBAT1U (0)
467 #define CONFIG_SYS_IBAT2L (0)
468 #define CONFIG_SYS_IBAT2U (0)
471 #ifdef CONFIG_MPC83XX_PCI2
472 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
474 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
476 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
477 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
478 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
481 #define CONFIG_SYS_IBAT3L (0)
482 #define CONFIG_SYS_IBAT3U (0)
483 #define CONFIG_SYS_IBAT4L (0)
484 #define CONFIG_SYS_IBAT4U (0)
487 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
488 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
489 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
490 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
493 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
494 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
496 #if (CONFIG_SYS_DDR_SIZE == 512)
497 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
498 BATL_PP_RW | BATL_MEMCOHERENCE)
499 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
500 BATU_BL_256M | BATU_VS | BATU_VP)
502 #define CONFIG_SYS_IBAT7L (0)
503 #define CONFIG_SYS_IBAT7U (0)
506 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
507 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
508 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
509 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
510 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
511 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
512 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
513 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
514 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
515 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
516 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
517 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
518 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
519 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
520 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
521 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
523 #if defined(CONFIG_CMD_KGDB)
524 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
528 * Environment Configuration
530 #define CONFIG_ENV_OVERWRITE
532 #if defined(CONFIG_TSEC_ENET)
533 #define CONFIG_HAS_ETH0
534 #define CONFIG_HAS_ETH1
537 #define CONFIG_HOSTNAME VME8349
538 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
539 #define CONFIG_BOOTFILE "uImage"
541 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
543 #undef CONFIG_BOOTARGS /* boot command will set bootargs */
545 #define CONFIG_BAUDRATE 9600
547 #define CONFIG_EXTRA_ENV_SETTINGS \
549 "hostname=vme8349\0" \
550 "nfsargs=setenv bootargs root=/dev/nfs rw " \
551 "nfsroot=${serverip}:${rootpath}\0" \
552 "ramargs=setenv bootargs root=/dev/ram rw\0" \
553 "addip=setenv bootargs ${bootargs} " \
554 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
555 ":${hostname}:${netdev}:off panic=1\0" \
556 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
557 "flash_nfs=run nfsargs addip addtty;" \
558 "bootm ${kernel_addr}\0" \
559 "flash_self=run ramargs addip addtty;" \
560 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
561 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
563 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
564 "update=protect off fff00000 fff3ffff; " \
565 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
566 "upd=run load update\0" \
568 "fdtfile=vme8349.dtb\0" \
571 #define CONFIG_NFSBOOTCOMMAND \
572 "setenv bootargs root=/dev/nfs rw " \
573 "nfsroot=$serverip:$rootpath " \
574 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
576 "console=$consoledev,$baudrate $othbootargs;" \
577 "tftp $loadaddr $bootfile;" \
578 "tftp $fdtaddr $fdtfile;" \
579 "bootm $loadaddr - $fdtaddr"
581 #define CONFIG_RAMBOOTCOMMAND \
582 "setenv bootargs root=/dev/ram rw " \
583 "console=$consoledev,$baudrate $othbootargs;" \
584 "tftp $ramdiskaddr $ramdiskfile;" \
585 "tftp $loadaddr $bootfile;" \
586 "tftp $fdtaddr $fdtfile;" \
587 "bootm $loadaddr $ramdiskaddr $fdtaddr"
589 #define CONFIG_BOOTCOMMAND "run flash_self"
592 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
593 unsigned char *buffer, int len);
596 #endif /* __CONFIG_H */