2 * esd vme8349 U-Boot configuration file
3 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
5 * (C) Copyright 2006-2010
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * reinhard.arlt@esd-electronics.de
9 * Based on the MPC8349EMDS config.
11 * SPDX-License-Identifier: GPL-2.0+
15 * vme8349 board configuration file.
21 #define CONFIG_DISPLAY_BOARDINFO
24 * Top level Makefile configuration choices
31 * High Level Configuration Options
33 #define CONFIG_E300 1 /* E300 Family */
34 #define CONFIG_MPC834x 1 /* MPC834x family */
35 #define CONFIG_MPC8349 1 /* MPC8349 specific */
36 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */
38 #define CONFIG_SYS_TEXT_BASE 0xFFF00000
40 #define CONFIG_MISC_INIT_R
43 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
44 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
46 #define CONFIG_PCI_66M
48 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
50 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
53 #ifndef CONFIG_SYS_CLK_FREQ
55 #define CONFIG_SYS_CLK_FREQ 66000000
56 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
58 #define CONFIG_SYS_CLK_FREQ 33000000
59 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
63 #define CONFIG_SYS_IMMR 0xE0000000
65 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
66 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
67 #define CONFIG_SYS_MEMTEST_END 0x00100000
72 #define CONFIG_DDR_ECC /* only for ECC DDR module */
73 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
74 #define CONFIG_SPD_EEPROM
75 #define SPD_EEPROM_ADDRESS 0x54
76 #define CONFIG_SYS_READ_SPD vme8349_read_spd
77 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
80 * 32-bit data path mode.
82 * Please note that using this mode for devices with the real density of 64-bit
83 * effectively reduces the amount of available memory due to the effect of
84 * wrapping around while translating address to row/columns, for example in the
85 * 256MB module the upper 128MB get aliased with contents of the lower
86 * 128MB); normally this define should be used for devices with real 32-bit
89 #undef CONFIG_DDR_32BIT
91 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
92 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
93 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
94 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
95 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
96 #define CONFIG_DDR_2T_TIMING
97 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
103 * FLASH on the Local Bus
105 #define CONFIG_SYS_FLASH_CFI
106 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
108 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
109 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
110 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
111 BR_PS_16 | /* 16bit */ \
112 BR_MS_GPCM | /* MSEL = GPCM */ \
115 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
125 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
126 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
128 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
129 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
130 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
131 BR_PS_16 | /* 16bit */ \
132 BR_MS_GPCM | /* MSEL = GPCM */ \
135 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
145 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
146 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
148 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
150 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
151 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
156 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
159 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
160 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
163 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
165 #undef CONFIG_SYS_FLASH_CHECKSUM
166 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
167 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
171 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
172 #define CONFIG_SYS_RAMBOOT
174 #undef CONFIG_SYS_RAMBOOT
177 #define CONFIG_SYS_INIT_RAM_LOCK 1
178 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
179 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
181 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
182 GENERATED_GBL_DATA_SIZE)
183 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
185 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
186 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
189 * Local Bus LCRR and LBCR regs
190 * LCRR: no DLL bypass, Clock divider is 4
191 * External Local Bus rate is
192 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
194 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
195 #define CONFIG_SYS_LBC_LBCR 0x00000000
197 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
202 #define CONFIG_CONS_INDEX 1
203 #define CONFIG_SYS_NS16550_SERIAL
204 #define CONFIG_SYS_NS16550_REG_SIZE 1
205 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
207 #define CONFIG_SYS_BAUDRATE_TABLE \
208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
210 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
211 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
213 #define CONFIG_CMDLINE_EDITING /* add command line history */
214 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
215 /* Use the HUSH parser */
216 #define CONFIG_SYS_HUSH_PARSER
219 #define CONFIG_SYS_I2C
220 #define CONFIG_SYS_I2C_FSL
221 #define CONFIG_SYS_FSL_I2C_SPEED 400000
222 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
223 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
224 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
225 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
226 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
227 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
228 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
230 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
233 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
234 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
235 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
236 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
240 * Addresses are mapped 1-1.
242 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
243 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
244 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
245 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
246 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
247 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
248 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
249 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
250 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
252 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
253 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
254 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
255 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
256 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
257 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
258 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
259 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
260 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
262 #if defined(CONFIG_PCI)
266 #if defined(PCI_64BIT)
274 #define CONFIG_PCI_PNP /* do pci plug-and-play */
276 #undef CONFIG_EEPRO100
279 #if !defined(CONFIG_PCI_PNP)
280 #define PCI_ENET0_IOADDR 0xFIXME
281 #define PCI_ENET0_MEMADDR 0xFIXME
282 #define PCI_IDSEL_NUMBER 0xFIXME
285 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
286 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
288 #endif /* CONFIG_PCI */
295 #define CONFIG_TSEC_ENET /* TSEC ethernet support */
298 #if defined(CONFIG_TSEC_ENET)
300 #define CONFIG_GMII /* MII PHY management */
302 #define CONFIG_TSEC1_NAME "TSEC0"
304 #define CONFIG_TSEC2_NAME "TSEC1"
305 #define CONFIG_PHY_M88E1111
306 #define TSEC1_PHY_ADDR 0x08
307 #define TSEC2_PHY_ADDR 0x10
308 #define TSEC1_PHYIDX 0
309 #define TSEC2_PHYIDX 0
310 #define TSEC1_FLAGS TSEC_GIGABIT
311 #define TSEC2_FLAGS TSEC_GIGABIT
313 /* Options are: TSEC[0-1] */
314 #define CONFIG_ETHPRIME "TSEC0"
316 #endif /* CONFIG_TSEC_ENET */
321 #ifndef CONFIG_SYS_RAMBOOT
322 #define CONFIG_ENV_IS_IN_FLASH
323 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
324 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
325 #define CONFIG_ENV_SIZE 0x2000
327 /* Address and size of Redundant Environment Sector */
328 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
329 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
332 #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
333 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
334 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
335 #define CONFIG_ENV_SIZE 0x2000
338 #define CONFIG_LOADS_ECHO /* echo on for serial download */
339 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
344 #define CONFIG_BOOTP_BOOTFILESIZE
345 #define CONFIG_BOOTP_BOOTPATH
346 #define CONFIG_BOOTP_GATEWAY
347 #define CONFIG_BOOTP_HOSTNAME
350 * Command line configuration.
352 #define CONFIG_CMD_I2C
353 #define CONFIG_CMD_MII
354 #define CONFIG_CMD_PING
355 #define CONFIG_CMD_DATE
356 #define CONFIG_SYS_RTC_BUS_NUM 0x01
357 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
358 #define CONFIG_RTC_RX8025
359 #define CONFIG_CMD_TSI148
361 #if defined(CONFIG_PCI)
362 #define CONFIG_CMD_PCI
365 #if defined(CONFIG_SYS_RAMBOOT)
366 #undef CONFIG_CMD_ENV
369 /* Pass Ethernet MAC to VxWorks */
370 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
372 #undef CONFIG_WATCHDOG /* watchdog disabled */
375 * Miscellaneous configurable options
377 #define CONFIG_SYS_LONGHELP /* undef to save memory */
378 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
380 #if defined(CONFIG_CMD_KGDB)
381 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
383 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
386 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
387 #define CONFIG_SYS_MAXARGS 16 /* max num of command args */
388 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buf Size */
391 * For booting Linux, the board info and command line data
392 * have to be in the first 256 MB of memory, since this is
393 * the maximum mapped by the Linux kernel during initialization.
395 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
397 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
399 #define CONFIG_SYS_HRCW_LOW (\
400 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
401 HRCWL_DDR_TO_SCB_CLK_1X1 |\
402 HRCWL_CSB_TO_CLKIN |\
404 HRCWL_CORE_TO_CSB_2X1)
406 #if defined(PCI_64BIT)
407 #define CONFIG_SYS_HRCW_HIGH (\
410 HRCWH_PCI1_ARBITER_ENABLE |\
411 HRCWH_PCI2_ARBITER_DISABLE |\
413 HRCWH_FROM_0X00000100 |\
414 HRCWH_BOOTSEQ_DISABLE |\
415 HRCWH_SW_WATCHDOG_DISABLE |\
416 HRCWH_ROM_LOC_LOCAL_16BIT |\
417 HRCWH_TSEC1M_IN_GMII |\
418 HRCWH_TSEC2M_IN_GMII)
420 #define CONFIG_SYS_HRCW_HIGH (\
423 HRCWH_PCI1_ARBITER_ENABLE |\
424 HRCWH_PCI2_ARBITER_ENABLE |\
426 HRCWH_FROM_0X00000100 |\
427 HRCWH_BOOTSEQ_DISABLE |\
428 HRCWH_SW_WATCHDOG_DISABLE |\
429 HRCWH_ROM_LOC_LOCAL_16BIT |\
430 HRCWH_TSEC1M_IN_GMII |\
431 HRCWH_TSEC2M_IN_GMII)
434 /* System IO Config */
435 #define CONFIG_SYS_SICRH 0
436 #define CONFIG_SYS_SICRL SICRL_LDP_A
438 #define CONFIG_SYS_HID0_INIT 0x000000000
439 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
440 HID0_ENABLE_INSTRUCTION_CACHE)
442 #define CONFIG_SYS_HID2 HID2_HBE
444 #define CONFIG_SYS_GPIO1_PRELIM
445 #define CONFIG_SYS_GPIO1_DIR 0x00100000
446 #define CONFIG_SYS_GPIO1_DAT 0x00100000
448 #define CONFIG_SYS_GPIO2_PRELIM
449 #define CONFIG_SYS_GPIO2_DIR 0x78900000
450 #define CONFIG_SYS_GPIO2_DAT 0x70100000
452 #define CONFIG_HIGH_BATS /* High BATs supported */
454 /* DDR @ 0x00000000 */
455 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
457 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
460 /* PCI @ 0x80000000 */
462 #define CONFIG_PCI_INDIRECT_BRIDGE
463 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
465 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
467 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
468 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
469 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
472 #define CONFIG_SYS_IBAT1L (0)
473 #define CONFIG_SYS_IBAT1U (0)
474 #define CONFIG_SYS_IBAT2L (0)
475 #define CONFIG_SYS_IBAT2U (0)
478 #ifdef CONFIG_MPC83XX_PCI2
479 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
481 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
483 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
484 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
485 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
488 #define CONFIG_SYS_IBAT3L (0)
489 #define CONFIG_SYS_IBAT3U (0)
490 #define CONFIG_SYS_IBAT4L (0)
491 #define CONFIG_SYS_IBAT4U (0)
494 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
495 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
496 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
497 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
500 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
501 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
503 #if (CONFIG_SYS_DDR_SIZE == 512)
504 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
505 BATL_PP_RW | BATL_MEMCOHERENCE)
506 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
507 BATU_BL_256M | BATU_VS | BATU_VP)
509 #define CONFIG_SYS_IBAT7L (0)
510 #define CONFIG_SYS_IBAT7U (0)
513 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
514 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
515 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
516 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
517 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
518 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
519 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
520 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
521 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
522 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
523 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
524 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
525 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
526 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
527 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
528 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
530 #if defined(CONFIG_CMD_KGDB)
531 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
535 * Environment Configuration
537 #define CONFIG_ENV_OVERWRITE
539 #if defined(CONFIG_TSEC_ENET)
540 #define CONFIG_HAS_ETH0
541 #define CONFIG_HAS_ETH1
544 #define CONFIG_HOSTNAME VME8349
545 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
546 #define CONFIG_BOOTFILE "uImage"
548 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
550 #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
551 #undef CONFIG_BOOTARGS /* boot command will set bootargs */
553 #define CONFIG_BAUDRATE 9600
555 #define CONFIG_EXTRA_ENV_SETTINGS \
557 "hostname=vme8349\0" \
558 "nfsargs=setenv bootargs root=/dev/nfs rw " \
559 "nfsroot=${serverip}:${rootpath}\0" \
560 "ramargs=setenv bootargs root=/dev/ram rw\0" \
561 "addip=setenv bootargs ${bootargs} " \
562 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
563 ":${hostname}:${netdev}:off panic=1\0" \
564 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
565 "flash_nfs=run nfsargs addip addtty;" \
566 "bootm ${kernel_addr}\0" \
567 "flash_self=run ramargs addip addtty;" \
568 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
569 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
571 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
572 "update=protect off fff00000 fff3ffff; " \
573 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
574 "upd=run load update\0" \
576 "fdtfile=vme8349.dtb\0" \
579 #define CONFIG_NFSBOOTCOMMAND \
580 "setenv bootargs root=/dev/nfs rw " \
581 "nfsroot=$serverip:$rootpath " \
582 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
584 "console=$consoledev,$baudrate $othbootargs;" \
585 "tftp $loadaddr $bootfile;" \
586 "tftp $fdtaddr $fdtfile;" \
587 "bootm $loadaddr - $fdtaddr"
589 #define CONFIG_RAMBOOTCOMMAND \
590 "setenv bootargs root=/dev/ram rw " \
591 "console=$consoledev,$baudrate $othbootargs;" \
592 "tftp $ramdiskaddr $ramdiskfile;" \
593 "tftp $loadaddr $bootfile;" \
594 "tftp $fdtaddr $fdtfile;" \
595 "bootm $loadaddr $ramdiskaddr $fdtaddr"
597 #define CONFIG_BOOTCOMMAND "run flash_self"
600 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
601 unsigned char *buffer, int len);
604 #endif /* __CONFIG_H */