1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * esd vme8349 U-Boot configuration file
4 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
6 * (C) Copyright 2006-2010
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * reinhard.arlt@esd-electronics.de
10 * Based on the MPC8349EMDS config.
14 * vme8349 board configuration file.
21 * Top level Makefile configuration choices
28 * High Level Configuration Options
30 #define CONFIG_E300 1 /* E300 Family */
31 #define CONFIG_MPC834x 1 /* MPC834x family */
32 #define CONFIG_MPC8349 1 /* MPC8349 specific */
33 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */
35 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
36 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
38 #define CONFIG_PCI_66M
40 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
42 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
45 #ifndef CONFIG_SYS_CLK_FREQ
47 #define CONFIG_SYS_CLK_FREQ 66000000
48 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
50 #define CONFIG_SYS_CLK_FREQ 33000000
51 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
55 #define CONFIG_SYS_IMMR 0xE0000000
57 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
58 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
59 #define CONFIG_SYS_MEMTEST_END 0x00100000
64 #define CONFIG_DDR_ECC /* only for ECC DDR module */
65 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
66 #define CONFIG_SPD_EEPROM
67 #define SPD_EEPROM_ADDRESS 0x54
68 #define CONFIG_SYS_READ_SPD vme8349_read_spd
69 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
72 * 32-bit data path mode.
74 * Please note that using this mode for devices with the real density of 64-bit
75 * effectively reduces the amount of available memory due to the effect of
76 * wrapping around while translating address to row/columns, for example in the
77 * 256MB module the upper 128MB get aliased with contents of the lower
78 * 128MB); normally this define should be used for devices with real 32-bit
81 #undef CONFIG_DDR_32BIT
83 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
84 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
85 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
86 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
87 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
88 #define CONFIG_DDR_2T_TIMING
89 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
95 * FLASH on the Local Bus
98 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
99 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
100 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
101 BR_PS_16 | /* 16bit */ \
102 BR_MS_GPCM | /* MSEL = GPCM */ \
105 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
115 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
116 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
118 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
119 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
120 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
121 BR_PS_16 | /* 16bit */ \
122 BR_MS_GPCM | /* MSEL = GPCM */ \
125 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
135 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
136 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
139 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
140 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
145 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
148 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
149 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
151 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
152 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
154 #undef CONFIG_SYS_FLASH_CHECKSUM
155 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
156 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
158 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
160 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
161 #define CONFIG_SYS_RAMBOOT
163 #undef CONFIG_SYS_RAMBOOT
166 #define CONFIG_SYS_INIT_RAM_LOCK 1
167 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
168 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
171 GENERATED_GBL_DATA_SIZE)
172 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
174 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
175 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
178 * Local Bus LCRR and LBCR regs
179 * LCRR: no DLL bypass, Clock divider is 4
180 * External Local Bus rate is
181 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
183 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
184 #define CONFIG_SYS_LBC_LBCR 0x00000000
186 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
191 #define CONFIG_SYS_NS16550_SERIAL
192 #define CONFIG_SYS_NS16550_REG_SIZE 1
193 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
195 #define CONFIG_SYS_BAUDRATE_TABLE \
196 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
198 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
199 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
202 #define CONFIG_SYS_I2C
203 #define CONFIG_SYS_I2C_FSL
204 #define CONFIG_SYS_FSL_I2C_SPEED 400000
205 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
206 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
207 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
208 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
209 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
210 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
211 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
213 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
216 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
217 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
218 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
219 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
223 * Addresses are mapped 1-1.
225 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
226 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
227 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
228 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
229 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
230 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
231 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
232 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
233 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
235 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
236 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
237 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
238 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
239 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
240 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
241 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
242 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
243 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
245 #if defined(CONFIG_PCI)
249 #if defined(PCI_64BIT)
255 #undef CONFIG_EEPRO100
258 #if !defined(CONFIG_PCI_PNP)
259 #define PCI_ENET0_IOADDR 0xFIXME
260 #define PCI_ENET0_MEMADDR 0xFIXME
261 #define PCI_IDSEL_NUMBER 0xFIXME
264 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
265 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
267 #endif /* CONFIG_PCI */
273 #if defined(CONFIG_TSEC_ENET)
275 #define CONFIG_GMII /* MII PHY management */
277 #define CONFIG_TSEC1_NAME "TSEC0"
279 #define CONFIG_TSEC2_NAME "TSEC1"
280 #define CONFIG_PHY_M88E1111
281 #define TSEC1_PHY_ADDR 0x08
282 #define TSEC2_PHY_ADDR 0x10
283 #define TSEC1_PHYIDX 0
284 #define TSEC2_PHYIDX 0
285 #define TSEC1_FLAGS TSEC_GIGABIT
286 #define TSEC2_FLAGS TSEC_GIGABIT
288 /* Options are: TSEC[0-1] */
289 #define CONFIG_ETHPRIME "TSEC0"
291 #endif /* CONFIG_TSEC_ENET */
296 #ifndef CONFIG_SYS_RAMBOOT
297 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
298 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
299 #define CONFIG_ENV_SIZE 0x2000
301 /* Address and size of Redundant Environment Sector */
302 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
303 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
306 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
307 #define CONFIG_ENV_SIZE 0x2000
310 #define CONFIG_LOADS_ECHO /* echo on for serial download */
311 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
316 #define CONFIG_BOOTP_BOOTFILESIZE
319 * Command line configuration.
321 #define CONFIG_SYS_RTC_BUS_NUM 0x01
322 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
323 #define CONFIG_RTC_RX8025
325 /* Pass Ethernet MAC to VxWorks */
326 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
328 #undef CONFIG_WATCHDOG /* watchdog disabled */
331 * Miscellaneous configurable options
333 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
336 * For booting Linux, the board info and command line data
337 * have to be in the first 256 MB of memory, since this is
338 * the maximum mapped by the Linux kernel during initialization.
340 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
342 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
344 #define CONFIG_SYS_HRCW_LOW (\
345 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
346 HRCWL_DDR_TO_SCB_CLK_1X1 |\
347 HRCWL_CSB_TO_CLKIN |\
349 HRCWL_CORE_TO_CSB_2X1)
351 #if defined(PCI_64BIT)
352 #define CONFIG_SYS_HRCW_HIGH (\
355 HRCWH_PCI1_ARBITER_ENABLE |\
356 HRCWH_PCI2_ARBITER_DISABLE |\
358 HRCWH_FROM_0X00000100 |\
359 HRCWH_BOOTSEQ_DISABLE |\
360 HRCWH_SW_WATCHDOG_DISABLE |\
361 HRCWH_ROM_LOC_LOCAL_16BIT |\
362 HRCWH_TSEC1M_IN_GMII |\
363 HRCWH_TSEC2M_IN_GMII)
365 #define CONFIG_SYS_HRCW_HIGH (\
368 HRCWH_PCI1_ARBITER_ENABLE |\
369 HRCWH_PCI2_ARBITER_ENABLE |\
371 HRCWH_FROM_0X00000100 |\
372 HRCWH_BOOTSEQ_DISABLE |\
373 HRCWH_SW_WATCHDOG_DISABLE |\
374 HRCWH_ROM_LOC_LOCAL_16BIT |\
375 HRCWH_TSEC1M_IN_GMII |\
376 HRCWH_TSEC2M_IN_GMII)
379 /* System IO Config */
380 #define CONFIG_SYS_SICRH 0
381 #define CONFIG_SYS_SICRL SICRL_LDP_A
383 #define CONFIG_SYS_HID0_INIT 0x000000000
384 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
385 HID0_ENABLE_INSTRUCTION_CACHE)
387 #define CONFIG_SYS_HID2 HID2_HBE
389 #define CONFIG_SYS_GPIO1_PRELIM
390 #define CONFIG_SYS_GPIO1_DIR 0x00100000
391 #define CONFIG_SYS_GPIO1_DAT 0x00100000
393 #define CONFIG_SYS_GPIO2_PRELIM
394 #define CONFIG_SYS_GPIO2_DIR 0x78900000
395 #define CONFIG_SYS_GPIO2_DAT 0x70100000
397 #define CONFIG_HIGH_BATS /* High BATs supported */
399 /* DDR @ 0x00000000 */
400 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
402 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
405 /* PCI @ 0x80000000 */
407 #define CONFIG_PCI_INDIRECT_BRIDGE
408 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
410 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
412 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
413 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
414 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
417 #define CONFIG_SYS_IBAT1L (0)
418 #define CONFIG_SYS_IBAT1U (0)
419 #define CONFIG_SYS_IBAT2L (0)
420 #define CONFIG_SYS_IBAT2U (0)
423 #ifdef CONFIG_MPC83XX_PCI2
424 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
426 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
428 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
429 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
430 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
433 #define CONFIG_SYS_IBAT3L (0)
434 #define CONFIG_SYS_IBAT3U (0)
435 #define CONFIG_SYS_IBAT4L (0)
436 #define CONFIG_SYS_IBAT4U (0)
439 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
440 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
441 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
442 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
445 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
446 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
448 #if (CONFIG_SYS_DDR_SIZE == 512)
449 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
450 BATL_PP_RW | BATL_MEMCOHERENCE)
451 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
452 BATU_BL_256M | BATU_VS | BATU_VP)
454 #define CONFIG_SYS_IBAT7L (0)
455 #define CONFIG_SYS_IBAT7U (0)
458 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
459 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
460 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
461 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
462 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
463 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
464 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
465 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
466 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
467 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
468 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
469 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
470 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
471 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
472 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
473 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
475 #if defined(CONFIG_CMD_KGDB)
476 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
480 * Environment Configuration
482 #define CONFIG_ENV_OVERWRITE
484 #if defined(CONFIG_TSEC_ENET)
485 #define CONFIG_HAS_ETH0
486 #define CONFIG_HAS_ETH1
489 #define CONFIG_HOSTNAME "VME8349"
490 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
491 #define CONFIG_BOOTFILE "uImage"
493 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
495 #define CONFIG_EXTRA_ENV_SETTINGS \
497 "hostname=vme8349\0" \
498 "nfsargs=setenv bootargs root=/dev/nfs rw " \
499 "nfsroot=${serverip}:${rootpath}\0" \
500 "ramargs=setenv bootargs root=/dev/ram rw\0" \
501 "addip=setenv bootargs ${bootargs} " \
502 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
503 ":${hostname}:${netdev}:off panic=1\0" \
504 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
505 "flash_nfs=run nfsargs addip addtty;" \
506 "bootm ${kernel_addr}\0" \
507 "flash_self=run ramargs addip addtty;" \
508 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
509 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
511 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
512 "update=protect off fff00000 fff3ffff; " \
513 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
514 "upd=run load update\0" \
516 "fdtfile=vme8349.dtb\0" \
519 #define CONFIG_NFSBOOTCOMMAND \
520 "setenv bootargs root=/dev/nfs rw " \
521 "nfsroot=$serverip:$rootpath " \
522 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
524 "console=$consoledev,$baudrate $othbootargs;" \
525 "tftp $loadaddr $bootfile;" \
526 "tftp $fdtaddr $fdtfile;" \
527 "bootm $loadaddr - $fdtaddr"
529 #define CONFIG_RAMBOOTCOMMAND \
530 "setenv bootargs root=/dev/ram rw " \
531 "console=$consoledev,$baudrate $othbootargs;" \
532 "tftp $ramdiskaddr $ramdiskfile;" \
533 "tftp $loadaddr $bootfile;" \
534 "tftp $fdtaddr $fdtfile;" \
535 "bootm $loadaddr $ramdiskaddr $fdtaddr"
537 #define CONFIG_BOOTCOMMAND "run flash_self"
540 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
541 unsigned char *buffer, int len);
544 #endif /* __CONFIG_H */