include/configs/vme8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * esd vme8349 U-Boot configuration file
   4  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   5  *
   6  * (C) Copyright 2006-2010
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * reinhard.arlt@esd-electronics.de
  10  * Based on the MPC8349EMDS config.
  11  */
  12
  13 /*
  14  * vme8349 board configuration file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * Top level Makefile configuration choices
  22  */
  23 #ifdef CONFIG_CADDY2
  24 #define VME_CADDY2
  25 #endif
  26
  27 /*
  28  * High Level Configuration Options
  29  */
  30 #define CONFIG_E300             1       /* E300 Family */
  31 #define CONFIG_VME8349          1       /* ESD VME8349 board specific */
  32
  33 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  34 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  35
  36 #define CONFIG_PCI_66M
  37 #ifdef CONFIG_PCI_66M
  38 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  39 #else
  40 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  41 #endif
  42
  43 #ifndef CONFIG_SYS_CLK_FREQ
  44 #ifdef CONFIG_PCI_66M
  45 #define CONFIG_SYS_CLK_FREQ     66000000
  46 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  47 #else
  48 #define CONFIG_SYS_CLK_FREQ     33000000
  49 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  50 #endif
  51 #endif
  52
  53 #define CONFIG_SYS_IMMR         0xE0000000
  54
  55 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  56 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  57 #define CONFIG_SYS_MEMTEST_END          0x00100000
  58
  59 /*
  60  * DDR Setup
  61  */
  62 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  63 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  64 #define CONFIG_SPD_EEPROM
  65 #define SPD_EEPROM_ADDRESS              0x54
  66 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  67 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  68
  69 /*
  70  * 32-bit data path mode.
  71  *
  72  * Please note that using this mode for devices with the real density of 64-bit
  73  * effectively reduces the amount of available memory due to the effect of
  74  * wrapping around while translating address to row/columns, for example in the
  75  * 256MB module the upper 128MB get aliased with contents of the lower
  76  * 128MB); normally this define should be used for devices with real 32-bit
  77  * data path.
  78  */
  79 #undef CONFIG_DDR_32BIT
  80
  81 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is sys memory*/
  82 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  83 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  84 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  85                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  86 #define CONFIG_DDR_2T_TIMING
  87 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  88                                         | DDRCDR_ODT \
  89                                         | DDRCDR_Q_DRN)
  90                                         /* 0x80080001 */
  91
  92 /*
  93  * FLASH on the Local Bus
  94  */
  95 #ifdef VME_CADDY2
  96 #define CONFIG_SYS_FLASH_BASE           0xffc00000      /* start of FLASH   */
  97 #define CONFIG_SYS_FLASH_SIZE           4               /* flash size in MB */
  98 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
  99                                          BR_PS_16 |     /*  16bit */ \
 100                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
 101                                          BR_V)          /* valid */
 102
 103 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 104                                         | OR_GPCM_XAM \
 105                                         | OR_GPCM_CSNT \
 106                                         | OR_GPCM_ACS_DIV2 \
 107                                         | OR_GPCM_XACS \
 108                                         | OR_GPCM_SCY_15 \
 109                                         | OR_GPCM_TRLX_SET \
 110                                         | OR_GPCM_EHTR_SET \
 111                                         | OR_GPCM_EAD)
 112                                         /* 0xffc06ff7 */
 113 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 114 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_4MB)
 115 #else
 116 #define CONFIG_SYS_FLASH_BASE           0xf8000000      /* start of FLASH   */
 117 #define CONFIG_SYS_FLASH_SIZE           128             /* flash size in MB */
 118 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | \
 119                                          BR_PS_16 |     /*  16bit */ \
 120                                          BR_MS_GPCM |   /*  MSEL = GPCM */ \
 121                                          BR_V)          /* valid */
 122
 123 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 124                                         | OR_GPCM_XAM \
 125                                         | OR_GPCM_CSNT \
 126                                         | OR_GPCM_ACS_DIV2 \
 127                                         | OR_GPCM_XACS \
 128                                         | OR_GPCM_SCY_15 \
 129                                         | OR_GPCM_TRLX_SET \
 130                                         | OR_GPCM_EHTR_SET \
 131                                         | OR_GPCM_EAD)
 132                                         /* 0xf8006ff7 */
 133 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 134 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 135 #endif
 136
 137 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
 138 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_WINDOW1_BASE \
 139                                         | BR_PS_32 \
 140                                         | BR_MS_GPCM \
 141                                         | BR_V)
 142                                         /* 0xF0001801 */
 143 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_256KB \
 144                                         | OR_GPCM_SETA)
 145                                         /* 0xfffc0208 */
 146 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_WINDOW1_BASE
 147 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_256KB)
 148
 149 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 150 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
 151
 152 #undef CONFIG_SYS_FLASH_CHECKSUM
 153 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
 154 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
 155
 156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 157
 158 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 159 #define CONFIG_SYS_RAMBOOT
 160 #else
 161 #undef CONFIG_SYS_RAMBOOT
 162 #endif
 163
 164 #define CONFIG_SYS_INIT_RAM_LOCK        1
 165 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
 166 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
 167
 168 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 169                                          GENERATED_GBL_DATA_SIZE)
 170 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 171
 172 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
 173 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
 174
 175 /*
 176  * Local Bus LCRR and LBCR regs
 177  *    LCRR:  no DLL bypass, Clock divider is 4
 178  * External Local Bus rate is
 179  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 180  */
 181 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 182 #define CONFIG_SYS_LBC_LBCR     0x00000000
 183
 184 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 185
 186 /*
 187  * Serial Port
 188  */
 189 #define CONFIG_SYS_NS16550_SERIAL
 190 #define CONFIG_SYS_NS16550_REG_SIZE     1
 191 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 192
 193 #define CONFIG_SYS_BAUDRATE_TABLE  \
 194                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 195
 196 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 197 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 198
 199 /* I2C */
 200 #define CONFIG_SYS_I2C
 201 #define CONFIG_SYS_I2C_FSL
 202 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 203 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 204 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 205 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 206 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 207 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 208 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 209 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 210
 211 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 212
 213 /* TSEC */
 214 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 215 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 216 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 217 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 218
 219 /*
 220  * General PCI
 221  * Addresses are mapped 1-1.
 222  */
 223 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 224 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 225 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 226 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 227 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 228 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 229 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 230 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 231 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 232
 233 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 234 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 235 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 236 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 237 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 238 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 239 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 240 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 241 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 242
 243 #if defined(CONFIG_PCI)
 244
 245 #define PCI_64BIT
 246 #define PCI_ONE_PCI1
 247 #if defined(PCI_64BIT)
 248 #undef PCI_ALL_PCI1
 249 #undef PCI_TWO_PCI1
 250 #undef PCI_ONE_PCI1
 251 #endif
 252
 253 #undef CONFIG_EEPRO100
 254 #undef CONFIG_TULIP
 255
 256 #if !defined(CONFIG_PCI_PNP)
 257         #define PCI_ENET0_IOADDR        0xFIXME
 258         #define PCI_ENET0_MEMADDR       0xFIXME
 259         #define PCI_IDSEL_NUMBER        0xFIXME
 260 #endif
 261
 262 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 263 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 264
 265 #endif  /* CONFIG_PCI */
 266
 267 /*
 268  * TSEC configuration
 269  */
 270
 271 #if defined(CONFIG_TSEC_ENET)
 272
 273 #define CONFIG_GMII                     /* MII PHY management */
 274 #define CONFIG_TSEC1
 275 #define CONFIG_TSEC1_NAME       "TSEC0"
 276 #define CONFIG_TSEC2
 277 #define CONFIG_TSEC2_NAME       "TSEC1"
 278 #define CONFIG_PHY_M88E1111
 279 #define TSEC1_PHY_ADDR          0x08
 280 #define TSEC2_PHY_ADDR          0x10
 281 #define TSEC1_PHYIDX            0
 282 #define TSEC2_PHYIDX            0
 283 #define TSEC1_FLAGS             TSEC_GIGABIT
 284 #define TSEC2_FLAGS             TSEC_GIGABIT
 285
 286 /* Options are: TSEC[0-1] */
 287 #define CONFIG_ETHPRIME         "TSEC0"
 288
 289 #endif  /* CONFIG_TSEC_ENET */
 290
 291 /*
 292  * Environment
 293  */
 294 #ifndef CONFIG_SYS_RAMBOOT
 295         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0xc0000)
 296         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 297         #define CONFIG_ENV_SIZE         0x2000
 298
 299 /* Address and size of Redundant Environment Sector     */
 300 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 301 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 302
 303 #else
 304         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 305         #define CONFIG_ENV_SIZE         0x2000
 306 #endif
 307
 308 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 309 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 310
 311 /*
 312  * BOOTP options
 313  */
 314 #define CONFIG_BOOTP_BOOTFILESIZE
 315
 316 /*
 317  * Command line configuration.
 318  */
 319 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 320 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 321 #define CONFIG_RTC_RX8025
 322
 323 /* Pass Ethernet MAC to VxWorks */
 324 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 325
 326 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 327
 328 /*
 329  * Miscellaneous configurable options
 330  */
 331 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 332
 333 /*
 334  * For booting Linux, the board info and command line data
 335  * have to be in the first 256 MB of memory, since this is
 336  * the maximum mapped by the Linux kernel during initialization.
 337  */
 338 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 339
 340 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 341
 342 #define CONFIG_SYS_HRCW_LOW (\
 343         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 344         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 345         HRCWL_CSB_TO_CLKIN |\
 346         HRCWL_VCO_1X2 |\
 347         HRCWL_CORE_TO_CSB_2X1)
 348
 349 #if defined(PCI_64BIT)
 350 #define CONFIG_SYS_HRCW_HIGH (\
 351         HRCWH_PCI_HOST |\
 352         HRCWH_64_BIT_PCI |\
 353         HRCWH_PCI1_ARBITER_ENABLE |\
 354         HRCWH_PCI2_ARBITER_DISABLE |\
 355         HRCWH_CORE_ENABLE |\
 356         HRCWH_FROM_0X00000100 |\
 357         HRCWH_BOOTSEQ_DISABLE |\
 358         HRCWH_SW_WATCHDOG_DISABLE |\
 359         HRCWH_ROM_LOC_LOCAL_16BIT |\
 360         HRCWH_TSEC1M_IN_GMII |\
 361         HRCWH_TSEC2M_IN_GMII)
 362 #else
 363 #define CONFIG_SYS_HRCW_HIGH (\
 364         HRCWH_PCI_HOST |\
 365         HRCWH_32_BIT_PCI |\
 366         HRCWH_PCI1_ARBITER_ENABLE |\
 367         HRCWH_PCI2_ARBITER_ENABLE |\
 368         HRCWH_CORE_ENABLE |\
 369         HRCWH_FROM_0X00000100 |\
 370         HRCWH_BOOTSEQ_DISABLE |\
 371         HRCWH_SW_WATCHDOG_DISABLE |\
 372         HRCWH_ROM_LOC_LOCAL_16BIT |\
 373         HRCWH_TSEC1M_IN_GMII |\
 374         HRCWH_TSEC2M_IN_GMII)
 375 #endif
 376
 377 /* System IO Config */
 378 #define CONFIG_SYS_SICRH 0
 379 #define CONFIG_SYS_SICRL SICRL_LDP_A
 380
 381 #define CONFIG_SYS_HID0_INIT    0x000000000
 382 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 383                                  HID0_ENABLE_INSTRUCTION_CACHE)
 384
 385 #define CONFIG_SYS_HID2         HID2_HBE
 386
 387 #define CONFIG_SYS_GPIO1_PRELIM
 388 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 389 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 390
 391 #define CONFIG_SYS_GPIO2_PRELIM
 392 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 393 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 394
 395 #define CONFIG_HIGH_BATS                /* High BATs supported */
 396
 397 /* DDR @ 0x00000000 */
 398 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 399                                  BATL_MEMCOHERENCE)
 400 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 401                                  BATU_VS | BATU_VP)
 402
 403 /* PCI @ 0x80000000 */
 404 #ifdef CONFIG_PCI
 405 #define CONFIG_PCI_INDIRECT_BRIDGE
 406 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
 407                                  BATL_MEMCOHERENCE)
 408 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
 409                                  BATU_VS | BATU_VP)
 410 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
 411                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 412 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
 413                                  BATU_VS | BATU_VP)
 414 #else
 415 #define CONFIG_SYS_IBAT1L       (0)
 416 #define CONFIG_SYS_IBAT1U       (0)
 417 #define CONFIG_SYS_IBAT2L       (0)
 418 #define CONFIG_SYS_IBAT2U       (0)
 419 #endif
 420
 421 #ifdef CONFIG_MPC83XX_PCI2
 422 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
 423                                  BATL_MEMCOHERENCE)
 424 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
 425                                  BATU_VS | BATU_VP)
 426 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
 427                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 428 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
 429                                  BATU_VS | BATU_VP)
 430 #else
 431 #define CONFIG_SYS_IBAT3L       (0)
 432 #define CONFIG_SYS_IBAT3U       (0)
 433 #define CONFIG_SYS_IBAT4L       (0)
 434 #define CONFIG_SYS_IBAT4U       (0)
 435 #endif
 436
 437 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 438 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 439                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 440 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | \
 441                                  BATU_VS | BATU_VP)
 442
 443 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
 444 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 445
 446 #if (CONFIG_SYS_DDR_SIZE == 512)
 447 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 448                                  BATL_PP_RW | BATL_MEMCOHERENCE)
 449 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
 450                                  BATU_BL_256M | BATU_VS | BATU_VP)
 451 #else
 452 #define CONFIG_SYS_IBAT7L       (0)
 453 #define CONFIG_SYS_IBAT7U       (0)
 454 #endif
 455
 456 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 457 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 458 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 459 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 460 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 461 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 462 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 463 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 464 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 465 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 466 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 467 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 468 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 469 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 470 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 471 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 472
 473 #if defined(CONFIG_CMD_KGDB)
 474 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 475 #endif
 476
 477 /*
 478  * Environment Configuration
 479  */
 480 #define CONFIG_ENV_OVERWRITE
 481
 482 #if defined(CONFIG_TSEC_ENET)
 483 #define CONFIG_HAS_ETH0
 484 #define CONFIG_HAS_ETH1
 485 #endif
 486
 487 #define CONFIG_HOSTNAME         "VME8349"
 488 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 489 #define CONFIG_BOOTFILE         "uImage"
 490
 491 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 492
 493 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 494         "netdev=eth0\0"                                                 \
 495         "hostname=vme8349\0"                                            \
 496         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 497                 "nfsroot=${serverip}:${rootpath}\0"                     \
 498         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 499         "addip=setenv bootargs ${bootargs} "                            \
 500                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 501                 ":${hostname}:${netdev}:off panic=1\0"                  \
 502         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 503         "flash_nfs=run nfsargs addip addtty;"                           \
 504                 "bootm ${kernel_addr}\0"                                \
 505         "flash_self=run ramargs addip addtty;"                          \
 506                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 507         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 508                 "bootm\0"                                               \
 509         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 510         "update=protect off fff00000 fff3ffff; "                        \
 511                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 512         "upd=run load update\0"                                         \
 513         "fdtaddr=780000\0"                                              \
 514         "fdtfile=vme8349.dtb\0"                                         \
 515         ""
 516
 517 #define CONFIG_NFSBOOTCOMMAND                                           \
 518         "setenv bootargs root=/dev/nfs rw "                             \
 519                 "nfsroot=$serverip:$rootpath "                          \
 520                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 521                                                         "$netdev:off "  \
 522                 "console=$consoledev,$baudrate $othbootargs;"           \
 523         "tftp $loadaddr $bootfile;"                                     \
 524         "tftp $fdtaddr $fdtfile;"                                       \
 525         "bootm $loadaddr - $fdtaddr"
 526
 527 #define CONFIG_RAMBOOTCOMMAND                                           \
 528         "setenv bootargs root=/dev/ram rw "                             \
 529                 "console=$consoledev,$baudrate $othbootargs;"           \
 530         "tftp $ramdiskaddr $ramdiskfile;"                               \
 531         "tftp $loadaddr $bootfile;"                                     \
 532         "tftp $fdtaddr $fdtfile;"                                       \
 533         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 534
 535 #define CONFIG_BOOTCOMMAND      "run flash_self"
 536
 537 #ifndef __ASSEMBLY__
 538 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 539                      unsigned char *buffer, int len);
 540 #endif
 541
 542 #endif  /* __CONFIG_H */