1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * esd vme8349 U-Boot configuration file
4 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
6 * (C) Copyright 2006-2010
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * reinhard.arlt@esd-electronics.de
10 * Based on the MPC8349EMDS config.
14 * vme8349 board configuration file.
21 * Top level Makefile configuration choices
28 * High Level Configuration Options
30 #define CONFIG_E300 1 /* E300 Family */
31 #define CONFIG_MPC834x 1 /* MPC834x family */
32 #define CONFIG_MPC8349 1 /* MPC8349 specific */
33 #define CONFIG_VME8349 1 /* ESD VME8349 board specific */
35 #define CONFIG_MISC_INIT_R
37 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
38 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
40 #define CONFIG_PCI_66M
42 #define CONFIG_83XX_CLKIN 66000000 /* in Hz */
44 #define CONFIG_83XX_CLKIN 33000000 /* in Hz */
47 #ifndef CONFIG_SYS_CLK_FREQ
49 #define CONFIG_SYS_CLK_FREQ 66000000
50 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
52 #define CONFIG_SYS_CLK_FREQ 33000000
53 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
57 #define CONFIG_SYS_IMMR 0xE0000000
59 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
60 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
61 #define CONFIG_SYS_MEMTEST_END 0x00100000
66 #define CONFIG_DDR_ECC /* only for ECC DDR module */
67 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
68 #define CONFIG_SPD_EEPROM
69 #define SPD_EEPROM_ADDRESS 0x54
70 #define CONFIG_SYS_READ_SPD vme8349_read_spd
71 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */
74 * 32-bit data path mode.
76 * Please note that using this mode for devices with the real density of 64-bit
77 * effectively reduces the amount of available memory due to the effect of
78 * wrapping around while translating address to row/columns, for example in the
79 * 256MB module the upper 128MB get aliased with contents of the lower
80 * 128MB); normally this define should be used for devices with real 32-bit
83 #undef CONFIG_DDR_32BIT
85 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
86 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
87 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
88 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
89 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
90 #define CONFIG_DDR_2T_TIMING
91 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \
97 * FLASH on the Local Bus
99 #define CONFIG_SYS_FLASH_CFI
100 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
102 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */
103 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */
104 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
105 BR_PS_16 | /* 16bit */ \
106 BR_MS_GPCM | /* MSEL = GPCM */ \
109 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
119 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
120 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB)
122 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
123 #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */
124 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
125 BR_PS_16 | /* 16bit */ \
126 BR_MS_GPCM | /* MSEL = GPCM */ \
129 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
139 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
140 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
142 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
144 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000
145 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \
150 #define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \
153 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE
154 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
156 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
157 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/
159 #undef CONFIG_SYS_FLASH_CHECKSUM
160 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */
161 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */
163 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
165 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
166 #define CONFIG_SYS_RAMBOOT
168 #undef CONFIG_SYS_RAMBOOT
171 #define CONFIG_SYS_INIT_RAM_LOCK 1
172 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */
173 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */
175 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
176 GENERATED_GBL_DATA_SIZE)
177 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
179 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */
180 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */
183 * Local Bus LCRR and LBCR regs
184 * LCRR: no DLL bypass, Clock divider is 4
185 * External Local Bus rate is
186 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
188 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
189 #define CONFIG_SYS_LBC_LBCR 0x00000000
191 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
196 #define CONFIG_SYS_NS16550_SERIAL
197 #define CONFIG_SYS_NS16550_REG_SIZE 1
198 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
200 #define CONFIG_SYS_BAUDRATE_TABLE \
201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
203 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
204 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
207 #define CONFIG_SYS_I2C
208 #define CONFIG_SYS_I2C_FSL
209 #define CONFIG_SYS_FSL_I2C_SPEED 400000
210 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
211 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
212 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
213 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
214 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
215 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
216 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
218 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */
221 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
222 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
223 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
224 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
228 * Addresses are mapped 1-1.
230 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
231 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
232 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
233 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
234 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
235 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
236 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
237 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
238 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
240 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
241 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
242 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
243 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
244 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
245 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
246 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
247 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
248 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
250 #if defined(CONFIG_PCI)
254 #if defined(PCI_64BIT)
260 #undef CONFIG_EEPRO100
263 #if !defined(CONFIG_PCI_PNP)
264 #define PCI_ENET0_IOADDR 0xFIXME
265 #define PCI_ENET0_MEMADDR 0xFIXME
266 #define PCI_IDSEL_NUMBER 0xFIXME
269 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
270 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
272 #endif /* CONFIG_PCI */
278 #if defined(CONFIG_TSEC_ENET)
280 #define CONFIG_GMII /* MII PHY management */
282 #define CONFIG_TSEC1_NAME "TSEC0"
284 #define CONFIG_TSEC2_NAME "TSEC1"
285 #define CONFIG_PHY_M88E1111
286 #define TSEC1_PHY_ADDR 0x08
287 #define TSEC2_PHY_ADDR 0x10
288 #define TSEC1_PHYIDX 0
289 #define TSEC2_PHYIDX 0
290 #define TSEC1_FLAGS TSEC_GIGABIT
291 #define TSEC2_FLAGS TSEC_GIGABIT
293 /* Options are: TSEC[0-1] */
294 #define CONFIG_ETHPRIME "TSEC0"
296 #endif /* CONFIG_TSEC_ENET */
301 #ifndef CONFIG_SYS_RAMBOOT
302 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000)
303 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
304 #define CONFIG_ENV_SIZE 0x2000
306 /* Address and size of Redundant Environment Sector */
307 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
308 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
311 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
312 #define CONFIG_ENV_SIZE 0x2000
315 #define CONFIG_LOADS_ECHO /* echo on for serial download */
316 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
321 #define CONFIG_BOOTP_BOOTFILESIZE
324 * Command line configuration.
326 #define CONFIG_SYS_RTC_BUS_NUM 0x01
327 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
328 #define CONFIG_RTC_RX8025
330 /* Pass Ethernet MAC to VxWorks */
331 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0
333 #undef CONFIG_WATCHDOG /* watchdog disabled */
336 * Miscellaneous configurable options
338 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
341 * For booting Linux, the board info and command line data
342 * have to be in the first 256 MB of memory, since this is
343 * the maximum mapped by the Linux kernel during initialization.
345 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/
347 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
349 #define CONFIG_SYS_HRCW_LOW (\
350 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
351 HRCWL_DDR_TO_SCB_CLK_1X1 |\
352 HRCWL_CSB_TO_CLKIN |\
354 HRCWL_CORE_TO_CSB_2X1)
356 #if defined(PCI_64BIT)
357 #define CONFIG_SYS_HRCW_HIGH (\
360 HRCWH_PCI1_ARBITER_ENABLE |\
361 HRCWH_PCI2_ARBITER_DISABLE |\
363 HRCWH_FROM_0X00000100 |\
364 HRCWH_BOOTSEQ_DISABLE |\
365 HRCWH_SW_WATCHDOG_DISABLE |\
366 HRCWH_ROM_LOC_LOCAL_16BIT |\
367 HRCWH_TSEC1M_IN_GMII |\
368 HRCWH_TSEC2M_IN_GMII)
370 #define CONFIG_SYS_HRCW_HIGH (\
373 HRCWH_PCI1_ARBITER_ENABLE |\
374 HRCWH_PCI2_ARBITER_ENABLE |\
376 HRCWH_FROM_0X00000100 |\
377 HRCWH_BOOTSEQ_DISABLE |\
378 HRCWH_SW_WATCHDOG_DISABLE |\
379 HRCWH_ROM_LOC_LOCAL_16BIT |\
380 HRCWH_TSEC1M_IN_GMII |\
381 HRCWH_TSEC2M_IN_GMII)
384 /* System IO Config */
385 #define CONFIG_SYS_SICRH 0
386 #define CONFIG_SYS_SICRL SICRL_LDP_A
388 #define CONFIG_SYS_HID0_INIT 0x000000000
389 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
390 HID0_ENABLE_INSTRUCTION_CACHE)
392 #define CONFIG_SYS_HID2 HID2_HBE
394 #define CONFIG_SYS_GPIO1_PRELIM
395 #define CONFIG_SYS_GPIO1_DIR 0x00100000
396 #define CONFIG_SYS_GPIO1_DAT 0x00100000
398 #define CONFIG_SYS_GPIO2_PRELIM
399 #define CONFIG_SYS_GPIO2_DIR 0x78900000
400 #define CONFIG_SYS_GPIO2_DAT 0x70100000
402 #define CONFIG_HIGH_BATS /* High BATs supported */
404 /* DDR @ 0x00000000 */
405 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
407 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
410 /* PCI @ 0x80000000 */
412 #define CONFIG_PCI_INDIRECT_BRIDGE
413 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \
415 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
417 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \
418 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
419 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
422 #define CONFIG_SYS_IBAT1L (0)
423 #define CONFIG_SYS_IBAT1U (0)
424 #define CONFIG_SYS_IBAT2L (0)
425 #define CONFIG_SYS_IBAT2U (0)
428 #ifdef CONFIG_MPC83XX_PCI2
429 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \
431 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \
433 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \
434 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
435 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \
438 #define CONFIG_SYS_IBAT3L (0)
439 #define CONFIG_SYS_IBAT3U (0)
440 #define CONFIG_SYS_IBAT4L (0)
441 #define CONFIG_SYS_IBAT4U (0)
444 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
445 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \
446 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
447 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \
450 #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE)
451 #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
453 #if (CONFIG_SYS_DDR_SIZE == 512)
454 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
455 BATL_PP_RW | BATL_MEMCOHERENCE)
456 #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \
457 BATU_BL_256M | BATU_VS | BATU_VP)
459 #define CONFIG_SYS_IBAT7L (0)
460 #define CONFIG_SYS_IBAT7U (0)
463 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
464 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
465 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
466 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
467 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
468 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
469 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
470 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
471 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
472 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
473 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
474 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
475 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
476 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
477 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
478 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
480 #if defined(CONFIG_CMD_KGDB)
481 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
485 * Environment Configuration
487 #define CONFIG_ENV_OVERWRITE
489 #if defined(CONFIG_TSEC_ENET)
490 #define CONFIG_HAS_ETH0
491 #define CONFIG_HAS_ETH1
494 #define CONFIG_HOSTNAME "VME8349"
495 #define CONFIG_ROOTPATH "/tftpboot/rootfs"
496 #define CONFIG_BOOTFILE "uImage"
498 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */
500 #define CONFIG_EXTRA_ENV_SETTINGS \
502 "hostname=vme8349\0" \
503 "nfsargs=setenv bootargs root=/dev/nfs rw " \
504 "nfsroot=${serverip}:${rootpath}\0" \
505 "ramargs=setenv bootargs root=/dev/ram rw\0" \
506 "addip=setenv bootargs ${bootargs} " \
507 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
508 ":${hostname}:${netdev}:off panic=1\0" \
509 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
510 "flash_nfs=run nfsargs addip addtty;" \
511 "bootm ${kernel_addr}\0" \
512 "flash_self=run ramargs addip addtty;" \
513 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
514 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
516 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \
517 "update=protect off fff00000 fff3ffff; " \
518 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
519 "upd=run load update\0" \
521 "fdtfile=vme8349.dtb\0" \
524 #define CONFIG_NFSBOOTCOMMAND \
525 "setenv bootargs root=/dev/nfs rw " \
526 "nfsroot=$serverip:$rootpath " \
527 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
529 "console=$consoledev,$baudrate $othbootargs;" \
530 "tftp $loadaddr $bootfile;" \
531 "tftp $fdtaddr $fdtfile;" \
532 "bootm $loadaddr - $fdtaddr"
534 #define CONFIG_RAMBOOTCOMMAND \
535 "setenv bootargs root=/dev/ram rw " \
536 "console=$consoledev,$baudrate $othbootargs;" \
537 "tftp $ramdiskaddr $ramdiskfile;" \
538 "tftp $loadaddr $bootfile;" \
539 "tftp $fdtaddr $fdtfile;" \
540 "bootm $loadaddr $ramdiskaddr $fdtaddr"
542 #define CONFIG_BOOTCOMMAND "run flash_self"
545 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
546 unsigned char *buffer, int len);
549 #endif /* __CONFIG_H */