2 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
4 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 * Configuration settings for the MX51-3Stack Freescale board.
8 * SPDX-License-Identifier: GPL-2.0+
15 #define CONFIG_MX51 /* in a mx51 */
16 #define CONFIG_SYS_TEXT_BASE 0x97800000
18 #include <asm/arch/imx-regs.h>
20 #define CONFIG_DISPLAY_CPUINFO
21 #define CONFIG_DISPLAY_BOARDINFO
23 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
24 #define CONFIG_SETUP_MEMORY_TAGS
25 #define CONFIG_INITRD_TAG
26 #define CONFIG_BOARD_LATE_INIT
28 #ifndef MACH_TYPE_TTC_VISION2
29 #define MACH_TYPE_TTC_VISION2 2775
31 #define CONFIG_MACH_TYPE MACH_TYPE_TTC_VISION2
34 * Size of malloc() pool
36 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
41 #define CONFIG_MXC_UART
42 #define CONFIG_MXC_UART_BASE UART3_BASE
43 #define CONFIG_MXC_GPIO
44 #define CONFIG_MXC_SPI
45 #define CONFIG_HW_WATCHDOG
53 #define CONFIG_SPI_FLASH
54 #define CONFIG_SPI_FLASH_STMICRO
57 * Use gpio 4 pin 25 as chip select for SPI flash
58 * This corresponds to gpio 121
60 #define CONFIG_SF_DEFAULT_CS 1
61 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
62 #define CONFIG_SF_DEFAULT_SPEED 25000000
64 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
65 #define CONFIG_ENV_SPI_BUS 0
66 #define CONFIG_ENV_SPI_MAX_HZ 25000000
67 #define CONFIG_ENV_SPI_MODE SPI_MODE_0
69 #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
70 #define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024)
71 #define CONFIG_ENV_SIZE (4 * 1024)
73 #define CONFIG_FSL_ENV_IN_SF
74 #define CONFIG_ENV_IS_IN_SPI_FLASH
78 #define CONFIG_POWER_SPI
79 #define CONFIG_POWER_FSL
80 #define CONFIG_FSL_PMIC_BUS 0
81 #define CONFIG_FSL_PMIC_CS 0
82 #define CONFIG_FSL_PMIC_CLK 2500000
83 #define CONFIG_FSL_PMIC_MODE SPI_MODE_0
84 #define CONFIG_FSL_PMIC_BITLEN 32
85 #define CONFIG_RTC_MC13XXX
90 #define CONFIG_FSL_ESDHC
91 #ifdef CONFIG_FSL_ESDHC
92 #define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000)
93 #define CONFIG_SYS_FSL_ESDHC_NUM 1
97 #define CONFIG_CMD_MMC
98 #define CONFIG_GENERIC_MMC
99 #define CONFIG_CMD_FAT
100 #define CONFIG_DOS_PARTITION
103 #define CONFIG_CMD_DATE
108 #define CONFIG_HAS_ETH1
111 #define CONFIG_FEC_MXC
112 #define IMX_FEC_BASE FEC_BASE_ADDR
113 #define CONFIG_FEC_MXC_PHYADDR 0x1F
115 #define CONFIG_CMD_PING
116 #define CONFIG_CMD_MII
117 #define CONFIG_CMD_NET
119 /* allow to overwrite serial and ethaddr */
120 #define CONFIG_ENV_OVERWRITE
121 #define CONFIG_CONS_INDEX 3
122 #define CONFIG_BAUDRATE 115200
124 /***********************************************************
126 ***********************************************************/
128 #include <config_cmd_default.h>
130 #define CONFIG_CMD_SPI
131 #undef CONFIG_CMD_IMLS
133 #define CONFIG_BOOTDELAY 3
135 #define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
137 #define CONFIG_EXTRA_ENV_SETTINGS \
139 "loadaddr=0x90800000\0"
142 * Miscellaneous configurable options
144 #define CONFIG_SYS_LONGHELP
145 #define CONFIG_SYS_PROMPT "Vision II U-boot > "
146 #define CONFIG_AUTO_COMPLETE
147 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
149 /* Print Buffer Size */
150 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
151 sizeof(CONFIG_SYS_PROMPT) + 16)
152 #define CONFIG_SYS_MAXARGS 64 /* max number of command args */
153 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
155 #define CONFIG_SYS_MEMTEST_START 0x90000000
156 #define CONFIG_SYS_MEMTEST_END 0x10000
158 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
160 #define CONFIG_CMDLINE_EDITING
161 #define CONFIG_SYS_HUSH_PARSER
164 * Physical Memory Map
166 #define CONFIG_NR_DRAM_BANKS 2
167 #define PHYS_SDRAM_1 CSD0_BASE_ADDR
168 #define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
169 #define PHYS_SDRAM_2 CSD1_BASE_ADDR
170 #define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024)
171 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
172 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
173 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
175 #define CONFIG_SYS_INIT_SP_OFFSET \
176 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
177 #define CONFIG_SYS_INIT_SP_ADDR \
178 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
180 #define CONFIG_BOARD_EARLY_INIT_F
182 /* 166 MHz DDR RAM */
183 #define CONFIG_SYS_DDR_CLKSEL 0
184 #define CONFIG_SYS_CLKTL_CBCDR 0x19239100
185 #define CONFIG_SYS_MAIN_PWR_ON
187 #define CONFIG_SYS_NO_FLASH
190 * Framebuffer and LCD
192 #define CONFIG_PREBOOT
194 #define CONFIG_VIDEO_IPUV3
195 #define CONFIG_CFB_CONSOLE
196 #define CONFIG_VGA_AS_SINGLE_DEVICE
197 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
198 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
199 #define CONFIG_VIDEO_BMP_RLE8
200 #define CONFIG_SPLASH_SCREEN
201 #define CONFIG_CMD_BMP
202 #define CONFIG_BMP_16BPP
203 #define CONFIG_IPUV3_CLK 133000000
205 #endif /* __CONFIG_H */