include/configs/vexpress_common.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2011 ARM Limited
   4  * (C) Copyright 2010 Linaro
   5  * Matt Waddel, <matt.waddel@linaro.org>
   6  *
   7  * Configuration for Versatile Express. Parts were derived from other ARM
   8  *   configurations.
   9  */
  10
  11 #ifndef __VEXPRESS_COMMON_H
  12 #define __VEXPRESS_COMMON_H
  13
  14 /*
  15  * Definitions copied from linux kernel:
  16  * arch/arm/mach-vexpress/include/mach/motherboard.h
  17  */
  18 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
  19 /* CS register bases for the original memory map. */
  20 #define V2M_PA_CS0              0x40000000
  21 #define V2M_PA_CS1              0x44000000
  22 #define V2M_PA_CS2              0x48000000
  23 #define V2M_PA_CS3              0x4c000000
  24 #define V2M_PA_CS7              0x10000000
  25
  26 #define V2M_PERIPH_OFFSET(x)    (x << 12)
  27 #define V2M_SYSREGS             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
  28 #define V2M_SYSCTL              (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
  29 #define V2M_SERIAL_BUS_PCI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
  30
  31 #define V2M_BASE                0x60000000
  32 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
  33 /* CS register bases for the extended memory map. */
  34 #define V2M_PA_CS0              0x08000000
  35 #define V2M_PA_CS1              0x0c000000
  36 #define V2M_PA_CS2              0x14000000
  37 #define V2M_PA_CS3              0x18000000
  38 #define V2M_PA_CS7              0x1c000000
  39
  40 #define V2M_PERIPH_OFFSET(x)    (x << 16)
  41 #define V2M_SYSREGS             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
  42 #define V2M_SYSCTL              (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
  43 #define V2M_SERIAL_BUS_PCI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
  44
  45 #define V2M_BASE                0x80000000
  46 #endif
  47
  48 /*
  49  * Physical addresses, offset from V2M_PA_CS0-3
  50  */
  51 #define V2M_NOR0                (V2M_PA_CS0)
  52 #define V2M_NOR1                (V2M_PA_CS1)
  53 #define V2M_SRAM                (V2M_PA_CS2)
  54 #define V2M_VIDEO_SRAM          (V2M_PA_CS3 + 0x00000000)
  55 #define V2M_ISP1761             (V2M_PA_CS3 + 0x03000000)
  56
  57 /* Common peripherals relative to CS7. */
  58 #define V2M_AACI                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
  59 #define V2M_KMI0                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
  60 #define V2M_KMI1                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
  61
  62 #define V2M_UART0               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
  63 #define V2M_UART1               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
  64 #define V2M_UART2               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
  65 #define V2M_UART3               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
  66
  67 #define V2M_WDT                 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
  68
  69 #define V2M_TIMER01             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
  70 #define V2M_TIMER23             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
  71
  72 #define V2M_SERIAL_BUS_DVI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
  73 #define V2M_RTC                 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
  74
  75 #define V2M_CF                  (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
  76
  77 #define V2M_CLCD                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
  78 #define V2M_SIZE_CS7            V2M_PERIPH_OFFSET(32)
  79
  80 /* System register offsets. */
  81 #define V2M_SYS_CFGDATA         (V2M_SYSREGS + 0x0a0)
  82 #define V2M_SYS_CFGCTRL         (V2M_SYSREGS + 0x0a4)
  83 #define V2M_SYS_CFGSTAT         (V2M_SYSREGS + 0x0a8)
  84
  85 /*
  86  * Configuration
  87  */
  88 #define SYS_CFG_START           (1 << 31)
  89 #define SYS_CFG_WRITE           (1 << 30)
  90 #define SYS_CFG_OSC             (1 << 20)
  91 #define SYS_CFG_VOLT            (2 << 20)
  92 #define SYS_CFG_AMP             (3 << 20)
  93 #define SYS_CFG_TEMP            (4 << 20)
  94 #define SYS_CFG_RESET           (5 << 20)
  95 #define SYS_CFG_SCC             (6 << 20)
  96 #define SYS_CFG_MUXFPGA         (7 << 20)
  97 #define SYS_CFG_SHUTDOWN        (8 << 20)
  98 #define SYS_CFG_REBOOT          (9 << 20)
  99 #define SYS_CFG_DVIMODE         (11 << 20)
 100 #define SYS_CFG_POWER           (12 << 20)
 101 #define SYS_CFG_SITE_MB         (0 << 16)
 102 #define SYS_CFG_SITE_DB1        (1 << 16)
 103 #define SYS_CFG_SITE_DB2        (2 << 16)
 104 #define SYS_CFG_STACK(n)        ((n) << 12)
 105
 106 #define SYS_CFG_ERR             (1 << 1)
 107 #define SYS_CFG_COMPLETE        (1 << 0)
 108
 109 /* Board info register */
 110 #define SYS_ID                          V2M_SYSREGS
 111 #define CONFIG_REVISION_TAG             1
 112
 113 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
 114 #define CONFIG_SETUP_MEMORY_TAGS        1
 115 #define CONFIG_SYS_L2CACHE_OFF          1
 116 #define CONFIG_INITRD_TAG               1
 117
 118 /* Size of malloc() pool */
 119 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */
 120
 121 #define SCTL_BASE                       V2M_SYSCTL
 122 #define VEXPRESS_FLASHPROG_FLVPPEN      (1 << 0)
 123
 124 #define CONFIG_SYS_TIMER_RATE           1000000
 125 #define CONFIG_SYS_TIMER_COUNTER        (V2M_TIMER01 + 0x4)
 126 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 127
 128 /* PL011 Serial Configuration */
 129 #define CONFIG_PL011_CLOCK              24000000
 130 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
 131                                          (void *)CONFIG_SYS_SERIAL1}
 132
 133 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 134 #define CONFIG_SYS_SERIAL0              V2M_UART0
 135 #define CONFIG_SYS_SERIAL1              V2M_UART1
 136
 137 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    127
 138
 139 /* BOOTP options */
 140 #define CONFIG_BOOTP_BOOTFILESIZE
 141
 142 /* Miscellaneous configurable options */
 143 #define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x8000)
 144 #define LINUX_BOOT_PARAM_ADDR           (V2M_BASE + 0x2000)
 145
 146 /* Physical Memory Map */
 147 #define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
 148 #define PHYS_SDRAM_2                    (((unsigned int)V2M_BASE) + \
 149                                         ((unsigned int)0x20000000))
 150 #define PHYS_SDRAM_1_SIZE               0x20000000      /* 512 MB */
 151 #define PHYS_SDRAM_2_SIZE               0x20000000      /* 512 MB */
 152
 153 /* additions for new relocation code */
 154 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 155 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000
 156 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_SDRAM_BASE + \
 157                                          CONFIG_SYS_INIT_RAM_SIZE - \
 158                                          GENERATED_GBL_DATA_SIZE)
 159 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_GBL_DATA_OFFSET
 160
 161 /* Basic environment settings */
 162 #define BOOT_TARGET_DEVICES(func) \
 163         func(MMC, mmc, 1) \
 164         func(MMC, mmc, 0) \
 165         func(PXE, pxe, na) \
 166         func(DHCP, dhcp, na)
 167 #include <config_distro_bootcmd.h>
 168
 169 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
 170 #define CONFIG_PLATFORM_ENV_SETTINGS \
 171                 "loadaddr=0x80008000\0" \
 172                 "ramdisk_addr_r=0x61000000\0" \
 173                 "kernel_addr=0x44100000\0" \
 174                 "ramdisk_addr=0x44800000\0" \
 175                 "maxramdisk=0x1800000\0" \
 176                 "pxefile_addr_r=0x88000000\0" \
 177                 "scriptaddr=0x88000000\0" \
 178                 "kernel_addr_r=0x80008000\0"
 179 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
 180 #define CONFIG_PLATFORM_ENV_SETTINGS \
 181                 "loadaddr=0xa0008000\0" \
 182                 "ramdisk_addr_r=0x81000000\0" \
 183                 "kernel_addr=0x0c100000\0" \
 184                 "ramdisk_addr=0x0c800000\0" \
 185                 "maxramdisk=0x1800000\0" \
 186                 "pxefile_addr_r=0xa8000000\0" \
 187                 "scriptaddr=0xa8000000\0" \
 188                 "kernel_addr_r=0xa0008000\0"
 189 #endif
 190 #define CONFIG_EXTRA_ENV_SETTINGS \
 191                 CONFIG_PLATFORM_ENV_SETTINGS \
 192                 BOOTENV \
 193                 "console=ttyAMA0,38400n8\0" \
 194                 "dram=1024M\0" \
 195                 "root=/dev/sda1 rw\0" \
 196                 "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
 197                         "24M@0x2000000(initrd)\0" \
 198                 "flashargs=setenv bootargs root=${root} console=${console} " \
 199                         "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
 200                         "devtmpfs.mount=0  vmalloc=256M\0" \
 201                 "bootflash=run flashargs; " \
 202                         "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
 203                         "bootm ${kernel_addr} ${ramdisk_addr_r}\0" \
 204                 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
 205
 206 /* FLASH and environment organization */
 207 #define PHYS_FLASH_SIZE                 0x04000000      /* 64MB */
 208 #define CONFIG_SYS_FLASH_SIZE           0x04000000
 209 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 210 #define CONFIG_SYS_FLASH_BASE0          V2M_NOR0
 211 #define CONFIG_SYS_FLASH_BASE1          V2M_NOR1
 212 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE0
 213
 214 /* Timeout values in ticks */
 215 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2 * CONFIG_SYS_HZ) /* Erase Timeout */
 216 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2 * CONFIG_SYS_HZ) /* Write Timeout */
 217
 218 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
 219 #define CONFIG_SYS_MAX_FLASH_SECT       259             /* Max sectors */
 220 #define FLASH_MAX_SECTOR_SIZE           0x00040000      /* 256 KB sectors */
 221
 222 /* Room required on the stack for the environment data */
 223
 224 /*
 225  * Amount of flash used for environment:
 226  * We don't know which end has the small erase blocks so we use the penultimate
 227  * sector location for the environment
 228  */
 229
 230 /* Store environment at top of flash */
 231 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* flinfo indicates empty blocks */
 232 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE0, \
 233                                           CONFIG_SYS_FLASH_BASE1 }
 234
 235 /* Monitor Command Prompt */
 236 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 237
 238 #endif /* VEXPRESS_COMMON_H */