include/configs/vexpress_common.h

   1 /*
   2  * (C) Copyright 2011 ARM Limited
   3  * (C) Copyright 2010 Linaro
   4  * Matt Waddel, <matt.waddel@linaro.org>
   5  *
   6  * Configuration for Versatile Express. Parts were derived from other ARM
   7  *   configurations.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __VEXPRESS_COMMON_H
  13 #define __VEXPRESS_COMMON_H
  14
  15 /*
  16  * Definitions copied from linux kernel:
  17  * arch/arm/mach-vexpress/include/mach/motherboard.h
  18  */
  19 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
  20 /* CS register bases for the original memory map. */
  21 #define V2M_PA_CS0              0x40000000
  22 #define V2M_PA_CS1              0x44000000
  23 #define V2M_PA_CS2              0x48000000
  24 #define V2M_PA_CS3              0x4c000000
  25 #define V2M_PA_CS7              0x10000000
  26
  27 #define V2M_PERIPH_OFFSET(x)    (x << 12)
  28 #define V2M_SYSREGS             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
  29 #define V2M_SYSCTL              (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
  30 #define V2M_SERIAL_BUS_PCI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
  31
  32 #define V2M_BASE                0x60000000
  33 #define CONFIG_SYS_TEXT_BASE    0x60800000
  34 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
  35 /* CS register bases for the extended memory map. */
  36 #define V2M_PA_CS0              0x08000000
  37 #define V2M_PA_CS1              0x0c000000
  38 #define V2M_PA_CS2              0x14000000
  39 #define V2M_PA_CS3              0x18000000
  40 #define V2M_PA_CS7              0x1c000000
  41
  42 #define V2M_PERIPH_OFFSET(x)    (x << 16)
  43 #define V2M_SYSREGS             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
  44 #define V2M_SYSCTL              (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
  45 #define V2M_SERIAL_BUS_PCI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
  46
  47 #define V2M_BASE                0x80000000
  48 #define CONFIG_SYS_TEXT_BASE    0x80800000
  49 #endif
  50
  51 /*
  52  * Physical addresses, offset from V2M_PA_CS0-3
  53  */
  54 #define V2M_NOR0                (V2M_PA_CS0)
  55 #define V2M_NOR1                (V2M_PA_CS1)
  56 #define V2M_SRAM                (V2M_PA_CS2)
  57 #define V2M_VIDEO_SRAM          (V2M_PA_CS3 + 0x00000000)
  58 #define V2M_ISP1761             (V2M_PA_CS3 + 0x03000000)
  59
  60 /* Common peripherals relative to CS7. */
  61 #define V2M_AACI                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
  62 #define V2M_MMCI                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
  63 #define V2M_KMI0                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
  64 #define V2M_KMI1                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
  65
  66 #define V2M_UART0               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
  67 #define V2M_UART1               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
  68 #define V2M_UART2               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
  69 #define V2M_UART3               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
  70
  71 #define V2M_WDT                 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
  72
  73 #define V2M_TIMER01             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
  74 #define V2M_TIMER23             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
  75
  76 #define V2M_SERIAL_BUS_DVI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
  77 #define V2M_RTC                 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
  78
  79 #define V2M_CF                  (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
  80
  81 #define V2M_CLCD                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
  82 #define V2M_SIZE_CS7            V2M_PERIPH_OFFSET(32)
  83
  84 /* System register offsets. */
  85 #define V2M_SYS_CFGDATA         (V2M_SYSREGS + 0x0a0)
  86 #define V2M_SYS_CFGCTRL         (V2M_SYSREGS + 0x0a4)
  87 #define V2M_SYS_CFGSTAT         (V2M_SYSREGS + 0x0a8)
  88
  89 /*
  90  * Configuration
  91  */
  92 #define SYS_CFG_START           (1 << 31)
  93 #define SYS_CFG_WRITE           (1 << 30)
  94 #define SYS_CFG_OSC             (1 << 20)
  95 #define SYS_CFG_VOLT            (2 << 20)
  96 #define SYS_CFG_AMP             (3 << 20)
  97 #define SYS_CFG_TEMP            (4 << 20)
  98 #define SYS_CFG_RESET           (5 << 20)
  99 #define SYS_CFG_SCC             (6 << 20)
 100 #define SYS_CFG_MUXFPGA         (7 << 20)
 101 #define SYS_CFG_SHUTDOWN        (8 << 20)
 102 #define SYS_CFG_REBOOT          (9 << 20)
 103 #define SYS_CFG_DVIMODE         (11 << 20)
 104 #define SYS_CFG_POWER           (12 << 20)
 105 #define SYS_CFG_SITE_MB         (0 << 16)
 106 #define SYS_CFG_SITE_DB1        (1 << 16)
 107 #define SYS_CFG_SITE_DB2        (2 << 16)
 108 #define SYS_CFG_STACK(n)        ((n) << 12)
 109
 110 #define SYS_CFG_ERR             (1 << 1)
 111 #define SYS_CFG_COMPLETE        (1 << 0)
 112
 113 /* Board info register */
 114 #define SYS_ID                          V2M_SYSREGS
 115 #define CONFIG_REVISION_TAG             1
 116
 117 #define CONFIG_SYS_MEMTEST_START        V2M_BASE
 118 #define CONFIG_SYS_MEMTEST_END          0x20000000
 119
 120 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
 121 #define CONFIG_SETUP_MEMORY_TAGS        1
 122 #define CONFIG_SYS_L2CACHE_OFF          1
 123 #define CONFIG_INITRD_TAG               1
 124
 125 /* Size of malloc() pool */
 126 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
 127
 128 #define SCTL_BASE                       V2M_SYSCTL
 129 #define VEXPRESS_FLASHPROG_FLVPPEN      (1 << 0)
 130
 131 #define CONFIG_SYS_TIMER_RATE           1000000
 132 #define CONFIG_SYS_TIMER_COUNTER        (V2M_TIMER01 + 0x4)
 133 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 134
 135 /* PL011 Serial Configuration */
 136 #define CONFIG_PL011_SERIAL
 137 #define CONFIG_PL011_CLOCK              24000000
 138 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
 139                                          (void *)CONFIG_SYS_SERIAL1}
 140 #define CONFIG_CONS_INDEX               0
 141
 142 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 143 #define CONFIG_SYS_SERIAL0              V2M_UART0
 144 #define CONFIG_SYS_SERIAL1              V2M_UART1
 145
 146 #define CONFIG_ARM_PL180_MMCI
 147 #define CONFIG_ARM_PL180_MMCI_BASE      V2M_MMCI
 148 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    127
 149 #define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
 150
 151 /* BOOTP options */
 152 #define CONFIG_BOOTP_BOOTFILESIZE
 153 #define CONFIG_BOOTP_BOOTPATH
 154 #define CONFIG_BOOTP_GATEWAY
 155 #define CONFIG_BOOTP_HOSTNAME
 156
 157 /* Miscellaneous configurable options */
 158 #define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x8000)
 159 #define LINUX_BOOT_PARAM_ADDR           (V2M_BASE + 0x2000)
 160
 161 /* Physical Memory Map */
 162 #define CONFIG_NR_DRAM_BANKS            2
 163 #define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
 164 #define PHYS_SDRAM_2                    (((unsigned int)V2M_BASE) + \
 165                                         ((unsigned int)0x20000000))
 166 #define PHYS_SDRAM_1_SIZE               0x20000000      /* 512 MB */
 167 #define PHYS_SDRAM_2_SIZE               0x20000000      /* 512 MB */
 168
 169 /* additions for new relocation code */
 170 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 171 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000
 172 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_SDRAM_BASE + \
 173                                          CONFIG_SYS_INIT_RAM_SIZE - \
 174                                          GENERATED_GBL_DATA_SIZE)
 175 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_GBL_DATA_OFFSET
 176
 177 #include <config_distro_defaults.h>
 178
 179 /* Basic environment settings */
 180 #define CONFIG_BOOTCOMMAND \
 181         "run distro_bootcmd; " \
 182         "run bootflash; "
 183
 184 #define BOOT_TARGET_DEVICES(func) \
 185         func(MMC, mmc, 1) \
 186         func(MMC, mmc, 0) \
 187         func(PXE, pxe, na) \
 188         func(DHCP, dhcp, na)
 189 #include <config_distro_bootcmd.h>
 190
 191 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
 192 #define CONFIG_PLATFORM_ENV_SETTINGS \
 193                 "loadaddr=0x80008000\0" \
 194                 "ramdisk_addr_r=0x61000000\0" \
 195                 "kernel_addr=0x44100000\0" \
 196                 "ramdisk_addr=0x44800000\0" \
 197                 "maxramdisk=0x1800000\0" \
 198                 "pxefile_addr_r=0x88000000\0" \
 199                 "scriptaddr=0x88000000\0" \
 200                 "kernel_addr_r=0x80008000\0"
 201 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
 202 #define CONFIG_PLATFORM_ENV_SETTINGS \
 203                 "loadaddr=0xa0008000\0" \
 204                 "ramdisk_addr_r=0x81000000\0" \
 205                 "kernel_addr=0x0c100000\0" \
 206                 "ramdisk_addr=0x0c800000\0" \
 207                 "maxramdisk=0x1800000\0" \
 208                 "pxefile_addr_r=0xa8000000\0" \
 209                 "scriptaddr=0xa8000000\0" \
 210                 "kernel_addr_r=0xa0008000\0"
 211 #endif
 212 #define CONFIG_EXTRA_ENV_SETTINGS \
 213                 CONFIG_PLATFORM_ENV_SETTINGS \
 214                 BOOTENV \
 215                 "console=ttyAMA0,38400n8\0" \
 216                 "dram=1024M\0" \
 217                 "root=/dev/sda1 rw\0" \
 218                 "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
 219                         "24M@0x2000000(initrd)\0" \
 220                 "flashargs=setenv bootargs root=${root} console=${console} " \
 221                         "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
 222                         "devtmpfs.mount=0  vmalloc=256M\0" \
 223                 "bootflash=run flashargs; " \
 224                         "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
 225                         "bootm ${kernel_addr} ${ramdisk_addr_r}\0"
 226
 227 /* FLASH and environment organization */
 228 #define PHYS_FLASH_SIZE                 0x04000000      /* 64MB */
 229 #define CONFIG_SYS_FLASH_CFI            1
 230 #define CONFIG_FLASH_CFI_DRIVER         1
 231 #define CONFIG_SYS_FLASH_SIZE           0x04000000
 232 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 233 #define CONFIG_SYS_FLASH_BASE0          V2M_NOR0
 234 #define CONFIG_SYS_FLASH_BASE1          V2M_NOR1
 235 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE0
 236
 237 /* Timeout values in ticks */
 238 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2 * CONFIG_SYS_HZ) /* Erase Timeout */
 239 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2 * CONFIG_SYS_HZ) /* Write Timeout */
 240
 241 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
 242 #define CONFIG_SYS_MAX_FLASH_SECT       259             /* Max sectors */
 243 #define FLASH_MAX_SECTOR_SIZE           0x00040000      /* 256 KB sectors */
 244
 245 /* Room required on the stack for the environment data */
 246 #define CONFIG_ENV_SIZE                 FLASH_MAX_SECTOR_SIZE
 247
 248 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
 249
 250 /*
 251  * Amount of flash used for environment:
 252  * We don't know which end has the small erase blocks so we use the penultimate
 253  * sector location for the environment
 254  */
 255 #define CONFIG_ENV_SECT_SIZE            FLASH_MAX_SECTOR_SIZE
 256 #define CONFIG_ENV_OVERWRITE            1
 257
 258 /* Store environment at top of flash */
 259 #define CONFIG_ENV_OFFSET               (PHYS_FLASH_SIZE - \
 260                                         (2 * CONFIG_ENV_SECT_SIZE))
 261 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE1 + \
 262                                          CONFIG_ENV_OFFSET)
 263 #define CONFIG_SYS_FLASH_PROTECTION     /* The devices have real protection */
 264 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* flinfo indicates empty blocks */
 265 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE0, \
 266                                           CONFIG_SYS_FLASH_BASE1 }
 267
 268 /* Monitor Command Prompt */
 269 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 270 #define CONFIG_SYS_LONGHELP
 271
 272 #endif /* VEXPRESS_COMMON_H */