include/configs/vexpress_common.h

   1 /*
   2  * (C) Copyright 2011 ARM Limited
   3  * (C) Copyright 2010 Linaro
   4  * Matt Waddel, <matt.waddel@linaro.org>
   5  *
   6  * Configuration for Versatile Express. Parts were derived from other ARM
   7  *   configurations.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef __VEXPRESS_COMMON_H
  13 #define __VEXPRESS_COMMON_H
  14
  15 /*
  16  * Definitions copied from linux kernel:
  17  * arch/arm/mach-vexpress/include/mach/motherboard.h
  18  */
  19 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
  20 /* CS register bases for the original memory map. */
  21 #define V2M_PA_CS0              0x40000000
  22 #define V2M_PA_CS1              0x44000000
  23 #define V2M_PA_CS2              0x48000000
  24 #define V2M_PA_CS3              0x4c000000
  25 #define V2M_PA_CS7              0x10000000
  26
  27 #define V2M_PERIPH_OFFSET(x)    (x << 12)
  28 #define V2M_SYSREGS             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
  29 #define V2M_SYSCTL              (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
  30 #define V2M_SERIAL_BUS_PCI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
  31
  32 #define V2M_BASE                0x60000000
  33 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
  34 /* CS register bases for the extended memory map. */
  35 #define V2M_PA_CS0              0x08000000
  36 #define V2M_PA_CS1              0x0c000000
  37 #define V2M_PA_CS2              0x14000000
  38 #define V2M_PA_CS3              0x18000000
  39 #define V2M_PA_CS7              0x1c000000
  40
  41 #define V2M_PERIPH_OFFSET(x)    (x << 16)
  42 #define V2M_SYSREGS             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
  43 #define V2M_SYSCTL              (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
  44 #define V2M_SERIAL_BUS_PCI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
  45
  46 #define V2M_BASE                0x80000000
  47 #endif
  48
  49 /*
  50  * Physical addresses, offset from V2M_PA_CS0-3
  51  */
  52 #define V2M_NOR0                (V2M_PA_CS0)
  53 #define V2M_NOR1                (V2M_PA_CS1)
  54 #define V2M_SRAM                (V2M_PA_CS2)
  55 #define V2M_VIDEO_SRAM          (V2M_PA_CS3 + 0x00000000)
  56 #define V2M_ISP1761             (V2M_PA_CS3 + 0x03000000)
  57
  58 /* Common peripherals relative to CS7. */
  59 #define V2M_AACI                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
  60 #define V2M_MMCI                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
  61 #define V2M_KMI0                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
  62 #define V2M_KMI1                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
  63
  64 #define V2M_UART0               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
  65 #define V2M_UART1               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
  66 #define V2M_UART2               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
  67 #define V2M_UART3               (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
  68
  69 #define V2M_WDT                 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
  70
  71 #define V2M_TIMER01             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
  72 #define V2M_TIMER23             (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
  73
  74 #define V2M_SERIAL_BUS_DVI      (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
  75 #define V2M_RTC                 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
  76
  77 #define V2M_CF                  (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
  78
  79 #define V2M_CLCD                (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
  80 #define V2M_SIZE_CS7            V2M_PERIPH_OFFSET(32)
  81
  82 /* System register offsets. */
  83 #define V2M_SYS_CFGDATA         (V2M_SYSREGS + 0x0a0)
  84 #define V2M_SYS_CFGCTRL         (V2M_SYSREGS + 0x0a4)
  85 #define V2M_SYS_CFGSTAT         (V2M_SYSREGS + 0x0a8)
  86
  87 /*
  88  * Configuration
  89  */
  90 #define SYS_CFG_START           (1 << 31)
  91 #define SYS_CFG_WRITE           (1 << 30)
  92 #define SYS_CFG_OSC             (1 << 20)
  93 #define SYS_CFG_VOLT            (2 << 20)
  94 #define SYS_CFG_AMP             (3 << 20)
  95 #define SYS_CFG_TEMP            (4 << 20)
  96 #define SYS_CFG_RESET           (5 << 20)
  97 #define SYS_CFG_SCC             (6 << 20)
  98 #define SYS_CFG_MUXFPGA         (7 << 20)
  99 #define SYS_CFG_SHUTDOWN        (8 << 20)
 100 #define SYS_CFG_REBOOT          (9 << 20)
 101 #define SYS_CFG_DVIMODE         (11 << 20)
 102 #define SYS_CFG_POWER           (12 << 20)
 103 #define SYS_CFG_SITE_MB         (0 << 16)
 104 #define SYS_CFG_SITE_DB1        (1 << 16)
 105 #define SYS_CFG_SITE_DB2        (2 << 16)
 106 #define SYS_CFG_STACK(n)        ((n) << 12)
 107
 108 #define SYS_CFG_ERR             (1 << 1)
 109 #define SYS_CFG_COMPLETE        (1 << 0)
 110
 111 /* Board info register */
 112 #define SYS_ID                          V2M_SYSREGS
 113 #define CONFIG_REVISION_TAG             1
 114
 115 #define CONFIG_SYS_MEMTEST_START        V2M_BASE
 116 #define CONFIG_SYS_MEMTEST_END          0x20000000
 117
 118 #define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
 119 #define CONFIG_SETUP_MEMORY_TAGS        1
 120 #define CONFIG_SYS_L2CACHE_OFF          1
 121 #define CONFIG_INITRD_TAG               1
 122
 123 /* Size of malloc() pool */
 124 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
 125
 126 #define SCTL_BASE                       V2M_SYSCTL
 127 #define VEXPRESS_FLASHPROG_FLVPPEN      (1 << 0)
 128
 129 #define CONFIG_SYS_TIMER_RATE           1000000
 130 #define CONFIG_SYS_TIMER_COUNTER        (V2M_TIMER01 + 0x4)
 131 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 132
 133 /* PL011 Serial Configuration */
 134 #define CONFIG_PL011_CLOCK              24000000
 135 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
 136                                          (void *)CONFIG_SYS_SERIAL1}
 137
 138 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 139 #define CONFIG_SYS_SERIAL0              V2M_UART0
 140 #define CONFIG_SYS_SERIAL1              V2M_UART1
 141
 142 #define CONFIG_ARM_PL180_MMCI
 143 #define CONFIG_ARM_PL180_MMCI_BASE      V2M_MMCI
 144 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    127
 145 #define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
 146
 147 /* BOOTP options */
 148 #define CONFIG_BOOTP_BOOTFILESIZE
 149
 150 /* Miscellaneous configurable options */
 151 #define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x8000)
 152 #define LINUX_BOOT_PARAM_ADDR           (V2M_BASE + 0x2000)
 153
 154 /* Physical Memory Map */
 155 #define CONFIG_NR_DRAM_BANKS            2
 156 #define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
 157 #define PHYS_SDRAM_2                    (((unsigned int)V2M_BASE) + \
 158                                         ((unsigned int)0x20000000))
 159 #define PHYS_SDRAM_1_SIZE               0x20000000      /* 512 MB */
 160 #define PHYS_SDRAM_2_SIZE               0x20000000      /* 512 MB */
 161
 162 /* additions for new relocation code */
 163 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 164 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000
 165 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_SDRAM_BASE + \
 166                                          CONFIG_SYS_INIT_RAM_SIZE - \
 167                                          GENERATED_GBL_DATA_SIZE)
 168 #define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SYS_GBL_DATA_OFFSET
 169
 170 /* Basic environment settings */
 171 #define BOOT_TARGET_DEVICES(func) \
 172         func(MMC, mmc, 1) \
 173         func(MMC, mmc, 0) \
 174         func(PXE, pxe, na) \
 175         func(DHCP, dhcp, na)
 176 #include <config_distro_bootcmd.h>
 177
 178 #ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
 179 #define CONFIG_PLATFORM_ENV_SETTINGS \
 180                 "loadaddr=0x80008000\0" \
 181                 "ramdisk_addr_r=0x61000000\0" \
 182                 "kernel_addr=0x44100000\0" \
 183                 "ramdisk_addr=0x44800000\0" \
 184                 "maxramdisk=0x1800000\0" \
 185                 "pxefile_addr_r=0x88000000\0" \
 186                 "scriptaddr=0x88000000\0" \
 187                 "kernel_addr_r=0x80008000\0"
 188 #elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
 189 #define CONFIG_PLATFORM_ENV_SETTINGS \
 190                 "loadaddr=0xa0008000\0" \
 191                 "ramdisk_addr_r=0x81000000\0" \
 192                 "kernel_addr=0x0c100000\0" \
 193                 "ramdisk_addr=0x0c800000\0" \
 194                 "maxramdisk=0x1800000\0" \
 195                 "pxefile_addr_r=0xa8000000\0" \
 196                 "scriptaddr=0xa8000000\0" \
 197                 "kernel_addr_r=0xa0008000\0"
 198 #endif
 199 #define CONFIG_EXTRA_ENV_SETTINGS \
 200                 CONFIG_PLATFORM_ENV_SETTINGS \
 201                 BOOTENV \
 202                 "console=ttyAMA0,38400n8\0" \
 203                 "dram=1024M\0" \
 204                 "root=/dev/sda1 rw\0" \
 205                 "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
 206                         "24M@0x2000000(initrd)\0" \
 207                 "flashargs=setenv bootargs root=${root} console=${console} " \
 208                         "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
 209                         "devtmpfs.mount=0  vmalloc=256M\0" \
 210                 "bootflash=run flashargs; " \
 211                         "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
 212                         "bootm ${kernel_addr} ${ramdisk_addr_r}\0"
 213
 214 /* FLASH and environment organization */
 215 #define PHYS_FLASH_SIZE                 0x04000000      /* 64MB */
 216 #define CONFIG_SYS_FLASH_CFI            1
 217 #define CONFIG_FLASH_CFI_DRIVER         1
 218 #define CONFIG_SYS_FLASH_SIZE           0x04000000
 219 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 220 #define CONFIG_SYS_FLASH_BASE0          V2M_NOR0
 221 #define CONFIG_SYS_FLASH_BASE1          V2M_NOR1
 222 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE0
 223
 224 /* Timeout values in ticks */
 225 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2 * CONFIG_SYS_HZ) /* Erase Timeout */
 226 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2 * CONFIG_SYS_HZ) /* Write Timeout */
 227
 228 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
 229 #define CONFIG_SYS_MAX_FLASH_SECT       259             /* Max sectors */
 230 #define FLASH_MAX_SECTOR_SIZE           0x00040000      /* 256 KB sectors */
 231
 232 /* Room required on the stack for the environment data */
 233 #define CONFIG_ENV_SIZE                 FLASH_MAX_SECTOR_SIZE
 234
 235 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
 236
 237 /*
 238  * Amount of flash used for environment:
 239  * We don't know which end has the small erase blocks so we use the penultimate
 240  * sector location for the environment
 241  */
 242 #define CONFIG_ENV_SECT_SIZE            FLASH_MAX_SECTOR_SIZE
 243 #define CONFIG_ENV_OVERWRITE            1
 244
 245 /* Store environment at top of flash */
 246 #define CONFIG_ENV_OFFSET               (PHYS_FLASH_SIZE - \
 247                                         (2 * CONFIG_ENV_SECT_SIZE))
 248 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE1 + \
 249                                          CONFIG_ENV_OFFSET)
 250 #define CONFIG_SYS_FLASH_PROTECTION     /* The devices have real protection */
 251 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* flinfo indicates empty blocks */
 252 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE0, \
 253                                           CONFIG_SYS_FLASH_BASE1 }
 254
 255 /* Monitor Command Prompt */
 256 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 257
 258 #endif /* VEXPRESS_COMMON_H */