include/configs/vexpress_aemv8a.h

   1 /*
   2  * Configuration for Versatile Express. Parts were derived from other ARM
   3  *   configurations.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __VEXPRESS_AEMV8A_H
   9 #define __VEXPRESS_AEMV8A_H
  10
  11 #ifdef CONFIG_BASE_FVP
  12 #ifndef CONFIG_SEMIHOSTING
  13 #error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING
  14 #endif
  15 #define CONFIG_BOARD_LATE_INIT
  16 #define CONFIG_ARMV8_SWITCH_TO_EL1
  17 #endif
  18
  19 #define CONFIG_REMAKE_ELF
  20
  21 #ifndef CONFIG_BASE_FVP
  22 /* Base FVP not using GICv3 yet */
  23 #define CONFIG_GICV3
  24 #endif
  25
  26 /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
  27
  28 /*#define CONFIG_SYS_GENERIC_BOARD*/
  29
  30 #define CONFIG_SYS_NO_FLASH
  31
  32 #define CONFIG_SUPPORT_RAW_INITRD
  33
  34 /* Cache Definitions */
  35 #define CONFIG_SYS_DCACHE_OFF
  36 #define CONFIG_SYS_ICACHE_OFF
  37
  38 #define CONFIG_IDENT_STRING             " vexpress_aemv8a"
  39 #define CONFIG_BOOTP_VCI_STRING         "U-boot.armv8.vexpress_aemv8a"
  40
  41 /* Link Definitions */
  42 #ifdef CONFIG_BASE_FVP
  43 /* ATF loads u-boot here for BASE_FVP model */
  44 #define CONFIG_SYS_TEXT_BASE            0x88000000
  45 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
  46 #else
  47 #define CONFIG_SYS_TEXT_BASE            0x80000000
  48 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  49 #endif
  50
  51 /* Flat Device Tree Definitions */
  52 #define CONFIG_OF_LIBFDT
  53
  54
  55 /* SMP Spin Table Definitions */
  56 #ifdef CONFIG_BASE_FVP
  57 #define CPU_RELEASE_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
  58 #else
  59 #define CPU_RELEASE_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  60 #endif
  61
  62 /* CS register bases for the original memory map. */
  63 #define V2M_PA_CS0                      0x00000000
  64 #define V2M_PA_CS1                      0x14000000
  65 #define V2M_PA_CS2                      0x18000000
  66 #define V2M_PA_CS3                      0x1c000000
  67 #define V2M_PA_CS4                      0x0c000000
  68 #define V2M_PA_CS5                      0x10000000
  69
  70 #define V2M_PERIPH_OFFSET(x)            (x << 16)
  71 #define V2M_SYSREGS                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
  72 #define V2M_SYSCTL                      (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
  73 #define V2M_SERIAL_BUS_PCI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
  74
  75 #define V2M_BASE                        0x80000000
  76
  77 /*
  78  * Physical addresses, offset from V2M_PA_CS0-3
  79  */
  80 #define V2M_NOR0                        (V2M_PA_CS0)
  81 #define V2M_NOR1                        (V2M_PA_CS4)
  82 #define V2M_SRAM                        (V2M_PA_CS1)
  83
  84 /* Common peripherals relative to CS7. */
  85 #define V2M_AACI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
  86 #define V2M_MMCI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
  87 #define V2M_KMI0                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
  88 #define V2M_KMI1                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
  89
  90 #define V2M_UART0                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
  91 #define V2M_UART1                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
  92 #define V2M_UART2                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
  93 #define V2M_UART3                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
  94
  95 #define V2M_WDT                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
  96
  97 #define V2M_TIMER01                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
  98 #define V2M_TIMER23                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
  99
 100 #define V2M_SERIAL_BUS_DVI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
 101 #define V2M_RTC                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
 102
 103 #define V2M_CF                          (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
 104
 105 #define V2M_CLCD                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
 106
 107 /* System register offsets. */
 108 #define V2M_SYS_CFGDATA                 (V2M_SYSREGS + 0x0a0)
 109 #define V2M_SYS_CFGCTRL                 (V2M_SYSREGS + 0x0a4)
 110 #define V2M_SYS_CFGSTAT                 (V2M_SYSREGS + 0x0a8)
 111
 112 /* Generic Timer Definitions */
 113 #define COUNTER_FREQUENCY               (0x1800000)     /* 24MHz */
 114
 115 /* Generic Interrupt Controller Definitions */
 116 #ifdef CONFIG_GICV3
 117 #define GICD_BASE                       (0x2f000000)
 118 #define GICR_BASE                       (0x2f100000)
 119 #else
 120
 121 #ifdef CONFIG_BASE_FVP
 122 #define GICD_BASE                       (0x2f000000)
 123 #define GICC_BASE                       (0x2c000000)
 124 #else
 125 #define GICD_BASE                       (0x2C001000)
 126 #define GICC_BASE                       (0x2C002000)
 127 #endif
 128 #endif
 129
 130 #define CONFIG_SYS_MEMTEST_START        V2M_BASE
 131 #define CONFIG_SYS_MEMTEST_END          (V2M_BASE + 0x80000000)
 132
 133 /* Size of malloc() pool */
 134 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (8 << 20))
 135
 136 /* SMSC91C111 Ethernet Configuration */
 137 #define CONFIG_SMC91111                 1
 138 #define CONFIG_SMC91111_BASE            (0x01A000000)
 139
 140 /* PL011 Serial Configuration */
 141 #define CONFIG_PL011_SERIAL
 142 #define CONFIG_PL011_CLOCK              24000000
 143 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
 144                                          (void *)CONFIG_SYS_SERIAL1}
 145 #define CONFIG_CONS_INDEX               0
 146
 147 #define CONFIG_BAUDRATE                 115200
 148 #define CONFIG_SYS_SERIAL0              V2M_UART0
 149 #define CONFIG_SYS_SERIAL1              V2M_UART1
 150
 151 /* Command line configuration */
 152 #define CONFIG_MENU
 153 /*#define CONFIG_MENU_SHOW*/
 154 #define CONFIG_CMD_CACHE
 155 #define CONFIG_CMD_BDI
 156 #define CONFIG_CMD_BOOTI
 157 #define CONFIG_CMD_UNZIP
 158 #define CONFIG_CMD_DHCP
 159 #define CONFIG_CMD_PXE
 160 #define CONFIG_CMD_ENV
 161 #define CONFIG_CMD_FLASH
 162 #define CONFIG_CMD_IMI
 163 #define CONFIG_CMD_MEMORY
 164 #define CONFIG_CMD_MII
 165 #define CONFIG_CMD_NET
 166 #define CONFIG_CMD_PING
 167 #define CONFIG_CMD_SAVEENV
 168 #define CONFIG_CMD_RUN
 169 #define CONFIG_CMD_BOOTD
 170 #define CONFIG_CMD_ECHO
 171 #define CONFIG_CMD_SOURCE
 172 #define CONFIG_CMD_FAT
 173 #define CONFIG_DOS_PARTITION
 174
 175 /* BOOTP options */
 176 #define CONFIG_BOOTP_BOOTFILESIZE
 177 #define CONFIG_BOOTP_BOOTPATH
 178 #define CONFIG_BOOTP_GATEWAY
 179 #define CONFIG_BOOTP_HOSTNAME
 180 #define CONFIG_BOOTP_PXE
 181 #define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
 182
 183 /* Miscellaneous configurable options */
 184 #define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x10000000)
 185
 186 /* Physical Memory Map */
 187 #define CONFIG_NR_DRAM_BANKS            1
 188 #define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
 189 #define PHYS_SDRAM_1_SIZE               0x80000000      /* 2048 MB */
 190 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 191
 192 /* Initial environment variables */
 193 #ifdef CONFIG_BASE_FVP
 194 #define CONFIG_EXTRA_ENV_SETTINGS       \
 195                                 "kernel_name=uImage\0"  \
 196                                 "kernel_addr_r=0x80000000\0"    \
 197                                 "initrd_name=ramdisk.img\0"     \
 198                                 "initrd_addr_r=0x88000000\0"    \
 199                                 "fdt_name=devtree.dtb\0"                \
 200                                 "fdt_addr_r=0x83000000\0"               \
 201                                 "fdt_high=0xffffffffffffffff\0" \
 202                                 "initrd_high=0xffffffffffffffff\0"
 203
 204 #define CONFIG_BOOTARGS         "console=ttyAMA0 earlyprintk=pl011,"\
 205                                 "0x1c090000 debug user_debug=31 "\
 206                                 "loglevel=9"
 207
 208 #define CONFIG_BOOTCOMMAND      "fdt addr $fdt_addr_r; fdt resize; " \
 209                                 "fdt chosen $initrd_addr_r $initrd_end; " \
 210                                 "bootm $kernel_addr_r - $fdt_addr_r"
 211
 212 #define CONFIG_BOOTDELAY                1
 213
 214 #else
 215
 216 #define CONFIG_EXTRA_ENV_SETTINGS       \
 217                                         "kernel_addr_r=0x80000000\0"    \
 218                                         "initrd_addr_r=0x88000000\0"    \
 219                                         "fdt_addr_r=0x83000000\0"               \
 220                                         "fdt_high=0xa0000000\0"
 221
 222 #define CONFIG_BOOTARGS                 "console=ttyAMA0 root=/dev/ram0"
 223 #define CONFIG_BOOTCOMMAND              "bootm $kernel_addr_r " \
 224                                         "$initrd_addr_r:$initrd_size $fdt_addr_r"
 225 #define CONFIG_BOOTDELAY                -1
 226 #endif
 227
 228 /* Do not preserve environment */
 229 #define CONFIG_ENV_IS_NOWHERE           1
 230 #define CONFIG_ENV_SIZE                 0x1000
 231
 232 /* Monitor Command Prompt */
 233 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 234 #define CONFIG_SYS_PROMPT               "VExpress64# "
 235 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 236                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 237 #define CONFIG_SYS_HUSH_PARSER
 238 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 239 #define CONFIG_SYS_LONGHELP
 240 #define CONFIG_CMDLINE_EDITING
 241 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 242
 243 #endif /* __VEXPRESS_AEMV8A_H */