1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration for Versatile Express. Parts were derived from other ARM
7 #ifndef __VEXPRESS_AEMV8A_H
8 #define __VEXPRESS_AEMV8A_H
10 #define CONFIG_REMAKE_ELF
12 /* Link Definitions */
13 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
14 /* ATF loads u-boot here for BASE_FVP model */
15 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
16 #elif CONFIG_TARGET_VEXPRESS64_JUNO
17 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
20 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
22 /* CS register bases for the original memory map. */
23 #define V2M_PA_CS0 0x00000000
24 #define V2M_PA_CS1 0x14000000
25 #define V2M_PA_CS2 0x18000000
26 #define V2M_PA_CS3 0x1c000000
27 #define V2M_PA_CS4 0x0c000000
28 #define V2M_PA_CS5 0x10000000
30 #define V2M_PERIPH_OFFSET(x) (x << 16)
31 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
32 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
33 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
35 #define V2M_BASE 0x80000000
37 /* Common peripherals relative to CS7. */
38 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
39 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
40 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
41 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
43 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
44 #define V2M_UART0 0x7ff80000
45 #define V2M_UART1 0x7ff70000
47 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
48 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
49 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
50 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
53 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
55 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
56 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
58 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
59 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
61 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
63 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
65 /* System register offsets. */
66 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
67 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
68 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
70 /* Generic Timer Definitions */
71 #define COUNTER_FREQUENCY 24000000 /* 24MHz */
73 /* Generic Interrupt Controller Definitions */
75 #define GICD_BASE (0x2f000000)
76 #define GICR_BASE (0x2f100000)
79 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
80 #define GICD_BASE (0x2f000000)
81 #define GICC_BASE (0x2c000000)
82 #elif CONFIG_TARGET_VEXPRESS64_JUNO
83 #define GICD_BASE (0x2C010000)
84 #define GICC_BASE (0x2C02f000)
86 #endif /* !CONFIG_GICV3 */
88 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO
89 /* The Vexpress64 simulators use SMSC91C111 */
90 #define CONFIG_SMC91111 1
91 #define CONFIG_SMC91111_BASE (0x01A000000)
94 /* PL011 Serial Configuration */
95 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
96 #define CONFIG_PL011_CLOCK 7372800
98 #define CONFIG_PL011_CLOCK 24000000
102 #define CONFIG_BOOTP_BOOTFILESIZE
104 /* Miscellaneous configurable options */
106 /* Physical Memory Map */
107 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
108 /* Top 16MB reserved for secure world use */
109 #define DRAM_SEC_SIZE 0x01000000
110 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
111 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
113 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
114 #define PHYS_SDRAM_2 (0x880000000)
115 #define PHYS_SDRAM_2_SIZE 0x180000000
116 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2
117 #define PHYS_SDRAM_2 (0x880000000)
118 #define PHYS_SDRAM_2_SIZE 0x80000000
123 /* Initial environment variables */
124 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
125 /* Copy the kernel and FDT to DRAM memory and boot */
126 #define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \
128 "afs load ${kernel_name} ${kernel_addr_r} ;"\
129 "if test $? -eq 1; then "\
130 " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\
131 " afs load ${kernel_alt_name} ${kernel_addr_r};"\
133 "afs load ${fdtfile} ${fdt_addr_r} ;"\
134 "if test $? -eq 1; then "\
135 " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\
136 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
138 "fdt addr ${fdt_addr_r}; fdt resize; " \
139 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
141 " setenv ramdisk_param ${ramdisk_addr_r}; "\
143 " setenv ramdisk_param -; "\
145 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0"
146 #define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs "
148 #define BOOT_TARGET_DEVICES(func) \
150 func(SATA, sata, 0) \
151 func(SATA, sata, 1) \
153 func(DHCP, dhcp, na) \
156 #include <config_distro_bootcmd.h>
159 * Defines where the kernel and FDT exist in NOR flash and where it will
160 * be copied into DRAM
162 #define CONFIG_EXTRA_ENV_SETTINGS \
163 "kernel_name=norkern\0" \
164 "kernel_alt_name=Image\0" \
165 "kernel_addr_r=0x80080000\0" \
166 "ramdisk_name=ramdisk.img\0" \
167 "ramdisk_addr_r=0x88000000\0" \
168 "fdtfile=board.dtb\0" \
169 "fdt_alt_name=juno\0" \
170 "fdt_addr_r=0x80000000\0" \
173 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
174 #define CONFIG_EXTRA_ENV_SETTINGS \
175 "kernel_name=Image\0" \
176 "kernel_addr=0x80080000\0" \
177 "initrd_name=ramdisk.img\0" \
178 "initrd_addr=0x88000000\0" \
179 "fdtfile=devtree.dtb\0" \
180 "fdt_addr=0x83000000\0" \
181 "boot_name=boot.img\0" \
182 "boot_addr=0x8007f800\0"
184 #ifndef CONFIG_BOOTCOMMAND
185 #define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \
187 " abootimg addr ${boot_addr}; " \
188 " abootimg get dtb --index=0 fdt_addr; " \
189 " bootm ${boot_addr} ${boot_addr} " \
192 " set fdt_high 0xffffffffffffffff; " \
193 " set initrd_high 0xffffffffffffffff; " \
194 " smhload ${kernel_name} ${kernel_addr}; " \
195 " smhload ${fdtfile} ${fdt_addr}; " \
196 " smhload ${initrd_name} ${initrd_addr} "\
198 " fdt addr ${fdt_addr}; fdt resize; " \
199 " fdt chosen ${initrd_addr} ${initrd_end}; " \
200 " booti $kernel_addr - $fdt_addr; " \
205 /* Monitor Command Prompt */
206 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
207 #define CONFIG_SYS_MAXARGS 64 /* max command args */
209 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
210 #define CONFIG_SYS_FLASH_BASE 0x08000000
211 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
212 #define CONFIG_SYS_MAX_FLASH_SECT 259
213 /* Store environment at top of flash in the same location as blank.img */
214 /* in the Juno firmware. */
216 #define CONFIG_SYS_FLASH_BASE 0x0C000000
217 /* 256 x 256KiB sectors */
218 #define CONFIG_SYS_MAX_FLASH_SECT 256
219 /* Store environment at top of flash */
222 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
223 #define CONFIG_SYS_MAX_FLASH_BANKS 1
225 #ifdef CONFIG_USB_EHCI_HCD
226 #define CONFIG_USB_OHCI_NEW
227 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
230 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
231 #define FLASH_MAX_SECTOR_SIZE 0x00040000
233 #endif /* __VEXPRESS_AEMV8A_H */