1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration for Versatile Express. Parts were derived from other ARM
7 #ifndef __VEXPRESS_AEMV8A_H
8 #define __VEXPRESS_AEMV8A_H
10 #define CONFIG_REMAKE_ELF
12 /* Link Definitions */
13 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
14 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
16 /* ATF loads u-boot here for BASE_FVP model */
17 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
20 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
22 /* CS register bases for the original memory map. */
23 #ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
24 #define V2M_BASE 0x00000000
25 #define V2M_PA_BASE 0x80000000
27 #define V2M_BASE 0x80000000
28 #define V2M_PA_BASE 0x00000000
31 #define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000)
32 #define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000)
33 #define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000)
34 #define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000)
35 #define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000)
36 #define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000)
38 #define V2M_PERIPH_OFFSET(x) (x << 16)
39 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
40 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
41 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
43 /* Common peripherals relative to CS7. */
44 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
45 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
46 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
47 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
49 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
50 #define V2M_UART0 0x7ff80000
51 #define V2M_UART1 0x7ff70000
53 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
54 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
55 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
56 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
59 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
61 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
62 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
64 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
65 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
67 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
69 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
71 /* System register offsets. */
72 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
73 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
74 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
76 /* Generic Timer Definitions */
77 #define COUNTER_FREQUENCY 100000000 /* 100MHz */
79 /* Generic Interrupt Controller Definitions */
81 #define GICD_BASE (V2M_PA_BASE + 0x2f000000)
82 #define GICR_BASE (V2M_PA_BASE + 0x2f100000)
85 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
86 #define GICD_BASE (0x2C010000)
87 #define GICC_BASE (0x2C02f000)
89 #define GICD_BASE (V2M_PA_BASE + 0x2f000000)
90 #define GICC_BASE (V2M_PA_BASE + 0x2c000000)
92 #endif /* !CONFIG_GICV3 */
94 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO
95 /* The Vexpress64 simulators use SMSC91C111 */
96 #define CONFIG_SMC91111 1
97 #define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000)
100 /* PL011 Serial Configuration */
101 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
102 #define CONFIG_PL011_CLOCK 7372800
104 #define CONFIG_PL011_CLOCK 24000000
108 #define CONFIG_BOOTP_BOOTFILESIZE
110 /* Miscellaneous configurable options */
112 /* Physical Memory Map */
113 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
114 /* Top 16MB reserved for secure world use */
115 #define DRAM_SEC_SIZE 0x01000000
116 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
117 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
119 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
120 #define PHYS_SDRAM_2 (0x880000000)
121 #define PHYS_SDRAM_2_SIZE 0x180000000
122 #elif CONFIG_NR_DRAM_BANKS == 2
123 #define PHYS_SDRAM_2 (0x880000000)
124 #define PHYS_SDRAM_2_SIZE 0x80000000
129 /* Initial environment variables */
130 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
131 /* Copy the kernel and FDT to DRAM memory and boot */
132 #define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \
134 "afs load ${kernel_name} ${kernel_addr_r} ;"\
135 "if test $? -eq 1; then "\
136 " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\
137 " afs load ${kernel_alt_name} ${kernel_addr_r};"\
139 "afs load ${fdtfile} ${fdt_addr_r} ;"\
140 "if test $? -eq 1; then "\
141 " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\
142 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
144 "fdt addr ${fdt_addr_r}; fdt resize; " \
145 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
147 " setenv ramdisk_param ${ramdisk_addr_r}; "\
149 " setenv ramdisk_param -; "\
151 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0"
152 #define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs "
154 #define BOOT_TARGET_DEVICES(func) \
156 func(SATA, sata, 0) \
157 func(SATA, sata, 1) \
159 func(DHCP, dhcp, na) \
162 #include <config_distro_bootcmd.h>
165 * Defines where the kernel and FDT exist in NOR flash and where it will
166 * be copied into DRAM
168 #define CONFIG_EXTRA_ENV_SETTINGS \
169 "kernel_name=norkern\0" \
170 "kernel_alt_name=Image\0" \
171 "kernel_addr_r=0x80080000\0" \
172 "ramdisk_name=ramdisk.img\0" \
173 "ramdisk_addr_r=0x88000000\0" \
174 "fdtfile=board.dtb\0" \
175 "fdt_alt_name=juno\0" \
176 "fdt_addr_r=0x80000000\0" \
179 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
180 #define CONFIG_EXTRA_ENV_SETTINGS \
181 "kernel_name=Image\0" \
182 "kernel_addr=0x80080000\0" \
183 "initrd_name=ramdisk.img\0" \
184 "initrd_addr=0x88000000\0" \
185 "fdtfile=devtree.dtb\0" \
186 "fdt_addr=0x83000000\0" \
187 "boot_name=boot.img\0" \
188 "boot_addr=0x8007f800\0"
190 #ifndef CONFIG_BOOTCOMMAND
191 #define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \
193 " abootimg addr ${boot_addr}; " \
194 " abootimg get dtb --index=0 fdt_addr; " \
195 " bootm ${boot_addr} ${boot_addr} " \
198 " set fdt_high 0xffffffffffffffff; " \
199 " set initrd_high 0xffffffffffffffff; " \
200 " smhload ${kernel_name} ${kernel_addr}; " \
201 " smhload ${fdtfile} ${fdt_addr}; " \
202 " smhload ${initrd_name} ${initrd_addr} "\
204 " fdt addr ${fdt_addr}; fdt resize; " \
205 " fdt chosen ${initrd_addr} ${initrd_end}; " \
206 " booti $kernel_addr - $fdt_addr; " \
210 #elif CONFIG_TARGET_VEXPRESS64_BASER_FVP
211 #define CONFIG_EXTRA_ENV_SETTINGS \
212 "kernel_addr=0x00800000\0" \
213 "fdt_addr=0x03000000\0" \
214 "boot_addr=0x0007f800\0"
217 /* Monitor Command Prompt */
218 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
219 #define CONFIG_SYS_MAXARGS 64 /* max command args */
221 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
222 #define CONFIG_SYS_FLASH_BASE 0x08000000
223 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
224 #define CONFIG_SYS_MAX_FLASH_SECT 259
225 /* Store environment at top of flash in the same location as blank.img */
226 /* in the Juno firmware. */
228 #define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
229 /* 256 x 256KiB sectors */
230 #define CONFIG_SYS_MAX_FLASH_SECT 256
231 /* Store environment at top of flash */
234 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
235 #define CONFIG_SYS_MAX_FLASH_BANKS 1
237 #ifdef CONFIG_USB_EHCI_HCD
238 #define CONFIG_USB_OHCI_NEW
239 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
242 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
243 #define FLASH_MAX_SECTOR_SIZE 0x00040000
245 #ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
246 #define CONFIG_ARMV8_SWITCH_TO_EL1
249 #endif /* __VEXPRESS_AEMV8A_H */