1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuration for Versatile Express. Parts were derived from other ARM
7 #ifndef __VEXPRESS_AEMV8_H
8 #define __VEXPRESS_AEMV8_H
10 #include <linux/stringify.h>
12 /* Link Definitions */
13 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
15 /* ATF loads u-boot here for BASE_FVP model */
18 /* CS register bases for the original memory map. */
19 #ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
20 #define V2M_DRAM_BASE 0x00000000
21 #define V2M_PA_BASE 0x80000000
23 #define V2M_DRAM_BASE 0x80000000
24 #define V2M_PA_BASE 0x00000000
27 #define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000)
28 #define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000)
29 #define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000)
30 #define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000)
31 #define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000)
32 #define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000)
34 #define V2M_PERIPH_OFFSET(x) (x << 16)
35 #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
36 #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
37 #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
39 /* Common peripherals relative to CS7. */
40 #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
41 #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
42 #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
43 #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
45 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
46 #define V2M_UART0 0x7ff80000
47 #define V2M_UART1 0x7ff70000
49 #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
50 #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
51 #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
52 #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
55 #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
57 #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
58 #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
60 #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
61 #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
63 #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
65 #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
67 /* System register offsets. */
68 #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
69 #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
70 #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
72 /* Generic Interrupt Controller Definitions */
74 #define GICD_BASE (V2M_PA_BASE + 0x2f000000)
75 #define GICR_BASE (V2M_PA_BASE + 0x2f100000)
78 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
79 #define GICD_BASE (0x2C010000)
80 #define GICC_BASE (0x2C02f000)
82 #define GICD_BASE (V2M_PA_BASE + 0x2f000000)
83 #define GICC_BASE (V2M_PA_BASE + 0x2c000000)
85 #endif /* !CONFIG_GICV3 */
87 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH)
88 /* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */
89 #define CONFIG_SMC91111 1
90 #define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000)
93 /* PL011 Serial Configuration */
94 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
95 #define CONFIG_PL011_CLOCK 7372800
97 #define CONFIG_PL011_CLOCK 24000000
100 /* Physical Memory Map */
101 #define PHYS_SDRAM_1 (V2M_DRAM_BASE) /* SDRAM Bank #1 */
102 /* Top 16MB reserved for secure world use */
103 #define DRAM_SEC_SIZE 0x01000000
104 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
105 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
107 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
108 #define PHYS_SDRAM_2 (0x880000000)
109 #define PHYS_SDRAM_2_SIZE 0x180000000
110 #elif CONFIG_NR_DRAM_BANKS == 2
111 #define PHYS_SDRAM_2 (0x880000000)
112 #define PHYS_SDRAM_2_SIZE 0x80000000
115 /* Copy the kernel, initrd and FDT from NOR flash to DRAM memory and boot. */
116 #define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \
118 "afs load ${kernel_name} ${kernel_addr_r} ;"\
119 "if test $? -eq 1; then "\
120 " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\
121 " afs load ${kernel_alt_name} ${kernel_addr_r};"\
123 "afs load ${fdtfile} ${fdt_addr_r} ;"\
124 "if test $? -eq 1; then "\
125 " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\
126 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
128 "fdt addr ${fdt_addr_r}; fdt resize; " \
129 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
131 " setenv ramdisk_param ${ramdisk_addr_r}; "\
133 " setenv ramdisk_param -; "\
135 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0"
136 #define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs "
138 /* Boot by executing a U-Boot script pre-loaded into DRAM. */
139 #define BOOTENV_DEV_MEM(devtypeu, devtypel, instance) \
141 "source ${scriptaddr}; " \
142 "if test $? -eq 1; then " \
143 " env import -t ${scriptaddr}; " \
144 " if test -n $uenvcmd; then " \
145 " echo Running uenvcmd ...; " \
149 #define BOOTENV_DEV_NAME_MEM(devtypeu, devtypel, instance) "mem "
151 #ifdef CONFIG_CMD_VIRTIO
152 #define FUNC_VIRTIO(func) func(VIRTIO, virtio, 0)
154 #define FUNC_VIRTIO(func)
158 * Boot by loading an Android image, or kernel, initrd and FDT through
159 * semihosting into DRAM.
161 #define BOOTENV_DEV_SMH(devtypeu, devtypel, instance) \
163 "if load hostfs - ${boot_addr_r} ${boot_name}; then" \
164 " setenv bootargs;" \
165 " abootimg addr ${boot_addr_r};" \
166 " abootimg get dtb --index=0 fdt_addr_r;" \
167 " bootm ${boot_addr_r} ${boot_addr_r} ${fdt_addr_r};" \
169 " if load hostfs - ${kernel_addr_r} ${kernel_name}; then" \
170 " setenv fdt_high 0xffffffffffffffff;" \
171 " setenv initrd_high 0xffffffffffffffff;" \
172 " load hostfs - ${fdt_addr_r} ${fdtfile};" \
173 " load hostfs - ${ramdisk_addr_r} ${ramdisk_name};" \
174 " fdt addr ${fdt_addr_r};" \
176 " fdt chosen ${ramdisk_addr_r} ${filesize};" \
177 " booti $kernel_addr_r - $fdt_addr_r;" \
180 #define BOOTENV_DEV_NAME_SMH(devtypeu, devtypel, instance) "smh "
182 /* Boot sources for distro boot and load addresses, per board */
184 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO /* Arm Juno board */
186 #define BOOT_TARGET_DEVICES(func) \
188 func(SATA, sata, 0) \
189 func(SATA, sata, 1) \
191 func(DHCP, dhcp, na) \
194 #define VEXPRESS_KERNEL_ADDR 0x80080000
195 #define VEXPRESS_PXEFILE_ADDR 0x8fb00000
196 #define VEXPRESS_FDT_ADDR 0x8fc00000
197 #define VEXPRESS_SCRIPT_ADDR 0x8fd00000
198 #define VEXPRESS_RAMDISK_ADDR 0x8fe00000
200 #define EXTRA_ENV_NAMES \
201 "kernel_name=norkern\0" \
202 "kernel_alt_name=Image\0" \
203 "ramdisk_name=ramdisk.img\0" \
204 "fdtfile=board.dtb\0" \
205 "fdt_alt_name=juno\0"
207 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ARMv8-A base model */
209 #define BOOT_TARGET_DEVICES(func) \
216 #define VEXPRESS_KERNEL_ADDR 0x80080000
217 #define VEXPRESS_PXEFILE_ADDR 0x8fa00000
218 #define VEXPRESS_SCRIPT_ADDR 0x8fb00000
219 #define VEXPRESS_FDT_ADDR 0x8fc00000
220 #define VEXPRESS_BOOT_ADDR 0x8fd00000
221 #define VEXPRESS_RAMDISK_ADDR 0x8fe00000
223 #define EXTRA_ENV_NAMES \
224 "kernel_name=Image\0" \
225 "ramdisk_name=ramdisk.img\0" \
226 "fdtfile=devtree.dtb\0" \
227 "boot_name=boot.img\0" \
228 "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0"
230 #elif CONFIG_TARGET_VEXPRESS64_BASER_FVP /* ARMv8-R base model */
232 #define BOOT_TARGET_DEVICES(func) \
238 #define VEXPRESS_KERNEL_ADDR 0x00200000
239 #define VEXPRESS_PXEFILE_ADDR 0x0fb00000
240 #define VEXPRESS_FDT_ADDR 0x0fc00000
241 #define VEXPRESS_SCRIPT_ADDR 0x0fd00000
242 #define VEXPRESS_RAMDISK_ADDR 0x0fe00000
244 #define EXTRA_ENV_NAMES \
245 "kernel_name=Image\0" \
246 "ramdisk_name=ramdisk.img\0" \
247 "fdtfile=board.dtb\0"
250 #include <config_distro_bootcmd.h>
252 /* Default load addresses and names for the different payloads. */
253 #define CONFIG_EXTRA_ENV_SETTINGS \
254 "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \
255 "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \
256 "pxefile_addr_r=" __stringify(VEXPRESS_PXEFILE_ADDR) "\0" \
257 "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \
258 "scriptaddr=" __stringify(VEXPRESS_SCRIPT_ADDR) "\0" \
262 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
263 #define CONFIG_SYS_FLASH_BASE 0x08000000
264 /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
265 #define CONFIG_SYS_MAX_FLASH_SECT 259
266 /* Store environment at top of flash in the same location as blank.img */
267 /* in the Juno firmware. */
269 #define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
270 /* 256 x 256KiB sectors */
271 #define CONFIG_SYS_MAX_FLASH_SECT 256
272 /* Store environment at top of flash */
275 #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
276 #define FLASH_MAX_SECTOR_SIZE 0x00040000
278 #endif /* __VEXPRESS_AEMV8_H */