1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2022 Toradex
6 #ifndef __VERDIN_IMX8MP_H
7 #define __VERDIN_IMX8MP_H
9 #include <asm/arch/imx-regs.h>
10 #include <linux/sizes.h>
12 #define CONFIG_SYS_MONITOR_LEN SZ_512K
13 #define CONFIG_SYS_UBOOT_BASE \
14 (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
16 #ifdef CONFIG_SPL_BUILD
17 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
19 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
20 #define CONFIG_MALLOC_F_ADDR 0x184000
21 /* For RAW image gives a error info not panic */
23 #define CONFIG_POWER_PCA9450
25 #define CONFIG_SYS_I2C
26 #endif /* CONFIG_SPL_BUILD */
30 #if defined(CONFIG_CMD_NET)
31 #define CONFIG_FEC_MXC_PHYADDR 7
33 #define PHY_ANEG_TIMEOUT 20000
34 #endif /* CONFIG_CMD_NET */
36 #define MEM_LAYOUT_ENV_SETTINGS \
37 "fdt_addr_r=0x50200000\0" \
38 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
39 "kernel_comp_addr_r=0x40200000\0" \
40 "kernel_comp_size=0x08080000\0" \
41 "ramdisk_addr_r=0x50300000\0" \
42 "scriptaddr=0x50280000\0"
44 /* Enable Distro Boot */
45 #define BOOT_TARGET_DEVICES(func) \
49 #include <config_distro_bootcmd.h>
51 #if defined(CONFIG_TDX_EASY_INSTALLER)
52 # define BOOT_SCRIPT "boot-tezi.scr"
54 # define BOOT_SCRIPT "boot.scr"
57 /* Initial environment variables */
58 #define CONFIG_EXTRA_ENV_SETTINGS \
60 MEM_LAYOUT_ENV_SETTINGS \
61 "bootcmd_mfg=fastboot 0\0" \
63 "boot_scripts=" BOOT_SCRIPT "\0" \
64 "boot_script_dhcp=" BOOT_SCRIPT "\0" \
67 "initrd_addr=0x43800000\0" \
68 "initrd_high=0xffffffffffffffff\0" \
69 "setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
70 "consoleblank=0 earlycon\0" \
71 "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
72 "if test \"$confirm\" = \"y\"; then " \
73 "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
74 "${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \
77 #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
78 #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
80 /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
81 #define CONFIG_SYS_SDRAM_BASE 0x40000000
82 #define PHYS_SDRAM 0x40000000
83 #define PHYS_SDRAM_SIZE (SZ_2G + SZ_1G)
84 #define PHYS_SDRAM_2 0x100000000
85 #define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G)
87 #endif /* __VERDIN_IMX8MP_H */