include/configs/verdin-imx8mp.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright 2022 Toradex
   4  */
   5
   6 #ifndef __VERDIN_IMX8MP_H
   7 #define __VERDIN_IMX8MP_H
   8
   9 #include <asm/arch/imx-regs.h>
  10 #include <linux/sizes.h>
  11
  12 #define CONFIG_SPL_MAX_SIZE                             (152 * 1024)
  13 #define CONFIG_SYS_MONITOR_LEN                          SZ_512K
  14 #define CONFIG_SYS_UBOOT_BASE   \
  15         (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
  16
  17 #ifdef CONFIG_SPL_BUILD
  18 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  19 #define CONFIG_SPL_STACK                0x960000
  20 #define CONFIG_SPL_BSS_START_ADDR       0x0098fc00
  21 #define CONFIG_SPL_BSS_MAX_SIZE         SZ_1K
  22 #define CONFIG_SYS_SPL_MALLOC_START     0x42200000
  23 #define CONFIG_SYS_SPL_MALLOC_SIZE      SZ_512K
  24
  25 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  26 #define CONFIG_MALLOC_F_ADDR                            0x184000
  27 /* For RAW image gives a error info not panic */
  28 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  29
  30 #define CONFIG_POWER_PCA9450
  31
  32 #define CONFIG_SYS_I2C
  33 #endif /* CONFIG_SPL_BUILD */
  34
  35 /* ENET Config */
  36 /* ENET1 */
  37 #if defined(CONFIG_CMD_NET)
  38 #define CONFIG_FEC_XCV_TYPE             RGMII
  39 #define CONFIG_FEC_MXC_PHYADDR          7
  40 #define FEC_QUIRK_ENET_MAC
  41
  42 #define PHY_ANEG_TIMEOUT 20000
  43 #endif /* CONFIG_CMD_NET */
  44
  45 #define MEM_LAYOUT_ENV_SETTINGS \
  46         "fdt_addr_r=0x43000000\0" \
  47         "kernel_addr_r=0x40000000\0" \
  48         "ramdisk_addr_r=0x46400000\0" \
  49         "scriptaddr=0x46000000\0"
  50
  51 /* Enable Distro Boot */
  52 #ifndef CONFIG_SPL_BUILD
  53 #define BOOT_TARGET_DEVICES(func) \
  54         func(MMC, mmc, 1) \
  55         func(MMC, mmc, 2) \
  56         func(DHCP, dhcp, na)
  57 #include <config_distro_bootcmd.h>
  58 #undef CONFIG_ISO_PARTITION
  59 #else
  60 #define BOOTENV
  61 #endif
  62
  63 #if defined(CONFIG_TDX_EASY_INSTALLER)
  64 #  define BOOT_SCRIPT   "boot-tezi.scr"
  65 #else
  66 #  define BOOT_SCRIPT   "boot.scr"
  67 #endif
  68
  69 /* Initial environment variables */
  70 #define CONFIG_EXTRA_ENV_SETTINGS \
  71         BOOTENV \
  72         MEM_LAYOUT_ENV_SETTINGS \
  73         "bootcmd_mfg=fastboot 0\0" \
  74         "boot_file=Image\0" \
  75         "boot_scripts=" BOOT_SCRIPT "\0" \
  76         "boot_script_dhcp=" BOOT_SCRIPT "\0" \
  77         "console=ttymxc2\0" \
  78         "fdt_board=dev\0" \
  79         "initrd_addr=0x43800000\0" \
  80         "initrd_high=0xffffffffffffffff\0" \
  81         "netargs=setenv bootargs console=${console},${baudrate} " \
  82                 "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
  83                 "\0" \
  84         "nfsboot=run netargs; dhcp ${loadaddr} ${boot_file}; " \
  85                 "tftp ${fdt_addr} verdin/${fdtfile}; " \
  86                 "booti ${loadaddr} - ${fdt_addr}\0" \
  87         "setup=setenv setupargs console=${console},${baudrate} console=tty1 " \
  88                 "consoleblank=0 earlycon\0" \
  89         "update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
  90                 "if test \"$confirm\" = \"y\"; then " \
  91                 "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
  92                 "${blkcnt} / 0x200; mmc dev 2 1; mmc write ${loadaddr} 0x0 " \
  93                 "${blkcnt}; fi\0"
  94
  95 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
  96 #define CONFIG_SYS_INIT_RAM_SIZE        SZ_512K
  97 #define CONFIG_SYS_INIT_SP_OFFSET \
  98         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  99 #define CONFIG_SYS_INIT_SP_ADDR \
 100         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 101
 102 #define CONFIG_SYS_BOOTM_LEN            SZ_64M /* Increase max gunzip size */
 103
 104 /* i.MX 8M Plus supports max. 8GB memory in two albeit concecutive banks */
 105 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 106 #define PHYS_SDRAM                      0x40000000
 107 #define PHYS_SDRAM_SIZE                 (SZ_2G + SZ_1G)
 108 #define PHYS_SDRAM_2                    0x100000000
 109 #define PHYS_SDRAM_2_SIZE               (SZ_4G + SZ_1G)
 110
 111 /* UART */
 112 #define CONFIG_MXC_UART_BASE            UART3_BASE_ADDR
 113
 114 /* Monitor Command Prompt */
 115 #define CONFIG_SYS_CBSIZE               SZ_2K
 116 #define CONFIG_SYS_MAXARGS              64
 117 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 118 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 119                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 120
 121 /* USDHC */
 122 #define CONFIG_SYS_FSL_USDHC_NUM        2
 123 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 124
 125 #endif /* __VERDIN_IMX8MP_H */